IEEE Circuits and Systems Magazine - Q2 2021 - 45

F. Big Data Frameworks Employing Accelerators
Although not widely supported yet, various academic
and industrial efforts exist that aim to incorporate heterogeneous
computing (e.g. Falcon computing targeting
both GPUs and FPGAs [58]) or at least a certain type of
accelerator into big data frameworks.
1) GPU
Compared to FPGAs, more work exists on supporting
GPUs from big data frameworks. There are a number of
reasons behind this. First, the GPU accelerator has been
steadily building popularity for a longer period of time
compared to FPGAs, and are more prevalent in datacenters
and supercomputers. Second, they have proven to
be very efficient in workloads related to machine learning.
Third, analytics frameworks, in their turn, often provide
very high-level libraries for machine learning due
to its rapidly growing popularity (an example is MLlib
for Apache Spark [59]). Targeting these high-level libraries
directly provides a clear insertion point for GPUs.
Although this approach will require serialization/deserialization
as is discussed in this work, this approach is
taken by several existing efforts [60]-[62].
The other approach used is to generate GPU code
from the execution graph, similar to what is done in this
work. The most well-known work is an industry project
by Nvidia called RAPIDS [63]-[65]. Academic efforts include
TensorFrame [66] and Spark-GPU [67].
2) FPGA
The open-source Blaze runtime system allows implementing
FPGA-accelerated algorithms for a Spark data
source [68]. Similar to the GPU work targeting high-level
Spark libraries, this does not allow accelerating queries
at the granularity of sub-stages in the execution graph,
giving it less flexibility and only allowing to implement
a whole algorithm on FPGA. The Kestrel Runtime from
Falcon Computing [58] is built on this runtime.
Related efforts taking the same approach as this work
include BigStream [69], which searches the Spark physical
execution plan for FPGA acceleration candidates
located in a bitstream store, and another novel project
integrating Intel's " Spark Native SQL Engine " [70] with
FPGAs [71].
As mentioned, FPGA usage in cloud instances is currently
very explicit, with clients needing to acquire a full
FPGA as opposed to CPU cycles that are much easier to
share with other users. An overview of efforts aiming to
virtualize FPGAs is presented in [72].
VII. Conclusion
In this article, we discussed our views on FPGA accelerators
for near-future big data analytics systems,
SECOND QUARTER 2021
their challenges and how to address them, as well as
the opportunities and how to leverage these. We also
presented a proposed architecture for a scalable but
still fully programmable system that can be built using
technologies that are currently becoming generally
available. We discussed the current difficulties involved
with designing custom accelerators for FPGAs
and how to improve design re-use and IP core connectivity
standardization by using Tydi and Tydal. We
present an analysis and evaluation of an FPGA-accelerated
big data prototype that makes use of several of
the discussed components.
While highly experimental, the prototype is able
to generate a high-performing FPGA circuit from very
high-level code descriptions in Spark. This is made possible
by specifically targeting the big data application
domain. This allows taking advantage of certain properties,
including the DAG representation that is used
internally in analytics frameworks and the highly parallel
programming language constructs such as Map,
filter and Reduce. These patterns are very suitable for
large compute clusters, but also map very naturally to a
spatial compute resource such as reconfigurable logic.
On a final note, within the context of Apache Spark and
Apache Arrow, a structured enough environment has
been contributed that allows for the automatic generation
of infrastructure for FPGA accelerators, without losing
potential performance advantage.
Acknowledgments
The authors would like to thank the reviewers and in
particular Hongbo Rong for the thoughtful review and
valuable comments. The authors also thank Patrick Lysaght
and Cathal McCabe from Xilinx for their support.
This work is part of the FitOptiVis project funded by the
ECSEL Joint Undertaking under grant number H2020ECSEL-2017-2-783162.
[73]
Joost Hoozemans Received his BSc in
Computer Science from Utrecht University
in 2011 and his MSc and PhD in Computer
Engineering from Delft University
of Technology in 2014 and 2018, respectively.
His research interests include VLIW
and TTA processors, reconfigurable computing and FPGA
programmability, and dataflow computing.
Johan Peltenburg is a Ph.D. candidate
with the Accelerated Big Data Systems
Group, TU Delft. He focuses on FPGA accelerators
for big data applications,
working on the Fletcher accelerator
framework. He is a member of IEEE.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
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