IEEE Circuits and Systems Magazine - Q2 2021 - 60

computation to achieve BA performance improvement.
The authors present a consensus framework
using the proximal splitting method to reduce the
computational cost. Similarly, Zhang et al. [154] propose
a distributed formulation to accelerate the global
BA computation without much distributed computing
communication overhead.
To better deploy BA in embedded systems with strict
power and real-time constraints, recent works explore
BA algorithm acceleration using specialized hardware.
The design in [155] implements both the image frontend
and BA backend of a VIO algorithm on a single-chip for
nano-drone scale applications. Liu et al. [156] propose a
hardware-software co-designed BA hardware accelerator
and its implementation on an embedded FPGA-SoC
to achieve higher performance and power efficiency
simultaneously. Especially, a co-observation optimization
technique and a hardware-friendly differentiation
method are proposed to accelerate BA operations with
optimized usage of memory and computation resources.
Sun et al. [157] present a hardware architecture running
local BA on FPGAs, which works without external
memory access and refines both cameras poses and 3D
map points simultaneously.
G. Discussion
We summarize FPGA based SLAM systems in Tab. III. It
only includes works that implement the whole SLAM on
an FPGA and provide overall performance and power
evaluation. The works in the table adopt a similar FPGASoC
architecture that accelerates computationally intensive
components by FPGA fabrics and offloads others
works to embedded processors on FPGAs. Compared
with sparse method, the semi-dense implementation
has lower frame rate, which is mainly due to the high
resolution data processed in the pipeline. Due to the
high frame rates and low power consumption, sparse
SLAM FPGA have been used in drones and autonomous
vehicles [16]. The two sparse SLAM implementations
achieve similar performance in terms of frame rate.
Compared with the ORB design, the VO SLAM design
includes pre-processing and outliers removal hardware,
such as image rectification and RANSAC, which lead to
a more accurate but power inefficient implementation.
Table III.
Comparison of FPGA SLAM Systems.
Method
Liu et al. [123]
Gu et al. [109]
60
V. Planning and Control on FPGA
A. Overview
Planning and control are the modules that compute how
the robot should maneuver itself. They usually include
behavioral decision, motion planning and feedback control
kernels. Without loss of generality, we focus on the
motion planning algorithms and their FPGA implementations
in this section.
As a fundamental problem in the robotic system, motion
planning aims to find the optimal collision-free path
from the current position to a goal position for a robot
in complex surroundings. Generally, motion planning
contains three steps, namely roadmap construction,
collision detection and graph search [38], [158]. Motion
planning will become a relatively complicated problem
when robots work with a high degree of freedom (DOF)
configurations since the search space will be exponentially
increased. Typically, state-of-the-art CPU-based
approaches take a few seconds to find a collision-free
trajectory [159]-[161], making the existing motion planning
algorithms too slow to meet the real-time requirement
for complex robot tasks and environments. Several
works have investigated approaches to speed up
motion planning, either for each stage or whole pipeline.
B. Roadmap Construction
In the roadmap construction step, the planner generates
a set of states in the robot's configuration space and
then connects them with edges to construct a generalpurpose
roadmap in the obstacle-free space. Each state
represents a robot's configuration, and each edge represents
a possible robot movement. Conventional algorithms
build the roadmap by randomly sampling poses
from configuration space at runtime to navigate around
the obstacles present at that time.
Several works explore roadmap construction accelerPlatform
Boikos
et al. [127] Semi Dense Xilinx Zynq 7020 SoC 4.5 fps
ORB
VO
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Xilinx Zynq 7000 SoC 31 fps
Altera Stratix III
31 fps
Frame Rate Power Indoor Error
2.5 W na
1.9 W 4.5 cm
5.9 W 2 cm
ation. Yershova et al. [162] improve the nearest neighbor
search to accelerate roadmap construction by orders
of magnitude compared to the naive nearest-neighbor
searching. Wang et al. [163] reduce the computation
workload by trimming roadmap edges and keeping the
roadmap to a reasonable size to achieve speedup. Different
from online runtime approaches, Murray et al. [164]
completely remove the
runtime latency by conducting
the roadmap
construction only once
at the design time. A
more general and much
larger roadmap is precomputed
and allows
for fast and successive
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