process, the configuration of SRAM FPGAs is only designated as " hardened " or simply having embedded SEE mitigation techniques rather than " hard, " which means close to immune [191]. Configuration SRAM is not used in the same way as the traditional SRAM. A bit flip in configuration causes an instantaneous effect without the need for a read-write cycle. Moreover, instead of producing one single error in the output, the bit flip shifts the user logic directly, changing the device's behavior. Scrubbing is needed to rectify SRAM configuration. Antifuse and flash FPGAs are less susceptible to effects in configuration and are designated " hard " against SEEs in their configuration without applying radiation hardening techniques [191]. Design based SEU/fault mitigation techniques are commonly used, for, in contrast to fabrication level radiation hardening techniques, they can be readily applied to commercial off the shelf (COTS) FPGAs. These techniques can be classified into static and dynamic. Static techniques rely on fault-masking, toleration of error without requiring active fixing. One such example