IEEE Circuits and Systems Magazine - Q2 2021 - 7

CAD tools fail to route some benchmarks on an architecture
are also often considered.
As an example, a key set of questions in FPGA architecture
is: What functionality should be hardened (i.e.
implemented as a new ASIC-style block) in the FPGA architecture?
How flexible should this block be? How much
of the FPGA die area should be dedicated to it? Ideally,
an FPGA architect would like the hardened functionality
to be usable by as many applications as possible at
the least possible silicon cost. An application that can
make use of the hard block will benefit by being smaller,
faster and more power-efficient than when implemented
solely in the programmable fabric. This motivates having
more programmability in the hard block to capture more
use cases; however, higher flexibility generally comes at
the cost of larger area and reduced efficiency of the hard
block. On the other hand, if a hard block is not usable
by an application circuit, its silicon area is wasted; the
FPGA user would rather have more of the usable generalpurpose
logic blocks in the area of the unused hard block.
The impact of this new hard block on the programmable
routing must also be considered-does it need more interconnect
or lead to slow routing paths to and from the block?
To evaluate whether a specific functionality should be hardened
or not, both the cost and gain
of hardening it have to be quantified
empirically using the flow described
in this section. FPGA architects may
try many ideas before landing on the
right combination of design choices
that adds just the right amount of
programmability in the right spots to
make this new hard block a net win.
In the following section, we detail
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many different components of FPGAs
and key architecture questions
for each. While we describe the key
results without detailing the experimental
methodology used to find
them, in general they came from a
holistic architecture evaluation flow
similar to that in Fig. 2.
III. FPGA Architecture Evolution
AND Array
A. Programmable Logic
The earliest reconfigurable computing
devices were programmable
array logic (PAL) architectures. PALs
consisted of an array of and gates
feeding another array of or gates,
as shown in Fig. 3, and could implement
any Boolean logic expression
SECOND QUARTER 2021
Outputs
O0
O1 O2 O3
as a two-level sum-of-products function. PALs achieve
configurability through programmable switches that select
the inputs to each of the and/or gates to implement
different Boolean expressions. The design tools for PALs
were very simple since the delay through the device is
constant no matter what logic function is implemented.
However, PALs do not scale well; as device logic capacity
increased, the wires forming the and/or arrays became
increasingly longer and slower and the number of programmable
switches required grew quadratically.
Subsequently, complex programmable logic devices
(CPLDs) kept the and/or arrays as the basic logic elements,
but attempted to solve the scalability challenge
by integrating multiple PALs on the same die with a
crossbar interconnect between them at the cost of more
complicated design tools. Shortly after, Xilinx pioneered
the first lookup-table-based (LUT-based) FPGA in 1984,
which consisted of an array of SRAM-based LUTs with
programmable interconnect between them. This style
of reconfigurable devices was shown to scale very well,
with LUTs achieving much higher area efficiency compared
to the and/or logic in PALs and CPLDs. Consequently,
LUT-based architectures became increasingly
dominant and today LUTs form the fundamental logic
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Inputs
OR Array
Figure 3. Programmable array logic (PAL) architecture with an and array feeding an or
array. The crosses are reconfigurable switches that are used to program any Boolean
expression as a two-level sum-of-products function.
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