element in all commercial FPGAs. Several research attempts [16]-[18] investigated replacing LUTs with a different form of configurable and gates: a full binary tree of and gates with programmable output/input inversion known as an and-inverter cone (AIC). However, when thoroughly evaluated in [19], AIC-based FPGA architectures had significantly larger area than LUT-based ones, A SRAMs Vdd B CD Input Buffers with delay gains only on small benchmarks that have short critical paths. A K-LUT can implement any K-input Boolean function by storing its truth table in configuration SRAM cells. K input signals are used as multiplexer select lines to choose an output from the 2K values of the truth table. Fig. 4(a) shows the transistor-level circuit implementation First Level I00 I10 Vdd Output Buffer Vdd Vdd Second Level (b) Vdd Ofeedback Orouting Internal Buffers (a) Local Crossbar Ofeedback Switch Block Multiplexer Basic Logic Element (BLE) (c) I01 I12 SRAMs ... I0N ... I1N Vdd IM0 IM1 ... IMN Output Buffer BLE 1 ... ... ... BLE 2 Orouting BLE N Logic Block (LB) ... ... ... I Inputs Connection Block Multiplexers Horizontal Routing (d) Figure 4. (a) Transistor-level implementation of a 4-LUT with internal buffers between the second and third LUT stages, (b) Two-level multiplexer circuitry, (c) Basic logic element (BLE), and (d) Logic block (LB) internal architecture. 8 IEEE CIRCUITS AND SYSTEMS MAGAZINE SECOND QUARTER 2021 Vertical Routing ... ... ... ... ... ... ... ... ... ... ... ... K Inputs K-LUT