IEEE Circuits and Systems Magazine - Q2 2021 - 84

two new kinds of resources:
an array of specialized
AI Engine processors and a
pervasive on-chip network
interconnect.
Each AI Engine processor
(Figure 7) is an independent
processor with it's
own 16 kB program memory
and 32 kB data memory.
The AI Engine architecture
is a highly parallel VLIW
processor capable of executing
up to 7 simultaneous,
independent instructions
scheduled to execute in
the same clock cycle. These
in structions can be scalar
instructions, executing on
the scalar datapath, or vector
instructions executing
on the vector datapath. For
instance, a complex VLIW
instruction could execute
2 vector loads, 1 vector store,
1 vector operation, 2 scalar
operations. Each processor
can be clocked at over
1 GHz and executes an independently
compiled C/
C++ program, avoiding concerns
about timing closure
common that can arise with
high-speed programmable
logic designs. Specialized
signal processing operations
including zero-overhead
loop instructions and
pointer-increment addressing
modes are also supported
to increase code density
and efficiency.
The AI Engine vector unit
implements one-dimensional
32-bit integer and fixed-point
SIMD operations executing
on each element of a 8 element
vector independently.
The output of the vector unit
can be accumulated in a special
wide vector accumulator
register. After a final result
is accumulated, it can be
84
IEEE CIRCUITS AND SYSTEMS MAGAZINE
SECOND QUARTER 2021
Adaptable Engines
2X Compute Density
AI Engines
Scalar Engines
* Platform Control
* Edge Compute
* AI Compute
* Diverse DSP Workloads
Network-on-Chipt
Protocol Engines
* Integrated 600 G Cores
* 4X Encrypted Bandwidth
Programmable I/O
* Any Interface or Sensor
* Includes 4.2 Gb/s MIPI
Transceivers
* Broad Range, 25 G→112 G
* 58 G in Mainstream Devices
PCIe and CCIX
* 2X PCIe and DMA Bandwidth
* Cache-Coherent Interface
to Accelerators
Figure 6. Xilinx' Versal architecture [15] is a heterogeneous integration of different compute blocks: (i) the scalar engines make up the processor subsystem of different types of ARM
Cortex cores, (ii) the adaptable engines are the traditional programmable logic, and (iii) the intelligent engines are an array of VLIW-vector processor; with a dedicated Network-onChip
connects the to each other and to the programmable I/O: DDR, HBM, PCIe, etc.
* Guaranteed Bandwidth
* Enables SW Programmability
DDR Memory
* 3200-DDR4, 3200-LPDDR4
* 2X Bandwidth/Pin

IEEE Circuits and Systems Magazine - Q2 2021

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