IEEE Circuits and Systems Magazine - Q2 2021 - 89
of 4550 images/second for sparse Resnet-50 model (85%
sparsity) at a batch size of one. A similar approach can
be used to implement dataflow with sparse layers using
Versal FPGA fabric, arrays of AI Engine processors or
combination of both.
C. Sparse Code Generation
Many DL applications and algorithms are trying to exploit
static sparsity by deploying sparse DNN models
(pruned network parameters) on emerging DL hardware
platforms. In the same way that dense convolutions can
be expressed as dense matrix-multiply operations, a
straightforward approach to implementing convolutions
with sparse weights is to leverage existing libraries for
sparse matrix-vector (SpMV) and sparse matrix-matrix
(SpMM) multiplication or to generate code specialized
for particular combinations of sparse and dense matrix
formats [72]. Unfortunately, while dense computations
typically exhibit significant data reuse enabling them to
scale easily, sparse computations often have less memory
locality and are more likely to be I/O bound.
Another approach is to add hardware support for
sparse [42], [54], [92], [117] or partially sparse matrices,
as is present in some modern GPUs, such as NVidia's
Ampere 100 [119] or Intel Movidius' Myriad [25]. This
technique allows the weight matrix to be a sparse matrix
that is specified only at runtime, as long as it meets
strict structural constraints. In Versal, these techniques
are well suited to implementation in programmable logic,
leveraging the network-on-chip to provide access to
external memory and the ability to specialize memory
and compute architectures to the characteristics of a
specific problem.
Although they are optimized for dense arithmetic operations,
AI Engine processors are also flexible enough
to implement some forms of sparse matrix processing.
Sparse matrix computation can be efficiently implemented
on these processors by generating code specialized
AIE
Conv2d 0
1
1
1
1
AIE
AIE
10
10
Conv2d 1
Conv2d 2
AIE
1
1
3
2
AIE
3
2
Figure 13. Example CNN with 3 layers mapped on 5 AI Engine processors leveraging a broadcast-cascade pattern. Different
weights sets are shown using different colors and channels within a weight set are labeled with numbers.
SECOND QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
89
IEEE Circuits and Systems Magazine - Q2 2021
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