IEEE Circuits and Systems Magazine - Q2 2021 - 96

[70] J. Kepner et al., " Sparse deep neural network graph challenge, " in
Proc. HPEC, 2019, pp. 1-7.
[71] J. Khan et al., " MIOpen: An open source library for deep learning
primitives, " 2019, arXiv:1910.00078.
[72] F. Kjolstad, S. Kamil, S. Chou, D. Lugato, and S. Amarasinghe, " The
tensor algebra compiler, " Proc. ACM Program. Lang., vol. 1, no. OOPSLA,
pp. 77:1-77:29, Oct. 2017. doi: 10.1145/3133901.
[73] A. Krizhevsky, I. Sutskever, and G. E. Hinton, " Imagenet classification
with deep convolutional neural networks, " in Proc. Adv. Neural
Inform. Process. Syst., Curran Associates, vol. 25, pp. 1097-1105, 2012.
[74] I. Kuon and J. Rose, " Measuring the gap between FPGAs and ASICs, "
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. (TCAD), vol. 26,
no. 2, pp. 203-215, 2007. doi: 10.1109/TCAD.2006.884574.
[75] C. Lattner and V. Adve, " LLVM: A compilation framework for lifelong
program analysis & transformation, " in Proc. Int. Symp. Code Generation
Optimization (CGO), 2004, p. 75.
[76] C. Lattner et al., " MLIR: A compiler infrastructure for the end of
Moore's law, " 2020, arXiv:2002.11054.
[77] N. Lee, T. Ajanthan, and P. Torr, " Snip: Single-shot network pruning
based on connection sensitivity, " in Proc. Int. Conf. Learn. Representations
(ICLR), 2019.
[78] P. Li et al., " Specification for the FIRRTL language, " Department
of Electrical Engineering and Computer Sciences, Univ. of California
Berkeley, Tech. Memorandum UCB/EECS-2016-9, 2016.
[79] S Lie, " Wafer scale deep learning, " in Proc. HotChips, 2019. [Online].
Available: https://old.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.
v02.pdf
[80] S. Liu and W. Deng, " Very deep convolutional neural network based
image classification using small training sample size, " in Proc. Asian
Conf. Pattern Recognit. (ACPR), 2015, pp. 730-734.
[81] W. Liu and B. Vinter, " A framework for general sparse matrix-matrix
multiplication on GPUs and heterogeneous processors, " J. Parallel
Distrib. Comput., vol. 85, pp. 47- 61, 2015. doi: 10.1016/j.jpdc.2015.06.010.
[82] P. Mattson et al., " MLPerf training benchmark, " 2020, arXiv:1910.01500.
[83] S.-I. Mirzadeh, M. Farajtabar, A. Li, N. Levine, A. Matsukawa, and H.
Ghasemzadeh, " Improved knowledge distillation via teacher assistant, "
2019, arXiv:1902.03393.
[84] S. Neuendorffer and K. Vissers, " Streaming systems in FPGAs, " in
Embedded Computer Systems: Architectures, Modeling, and Simulation
(SAMOS), Springer Berlin Heidelberg, 2008, pp. 147-156.
[85] G. Nguyen et al., " Machine learning and deep learning frameworks
and libraries for large-scale data mining: A survey, " Artif. Intell. Rev.,
vol. 52, no. 1, pp. 77-124, 2019. doi: 10.1007/s10462-018-09679-z.
[86] R Nigam et al., " Predictable accelerator design with time-sensitive
affine types, " in Proc. Conf. Programming Language Design Implementation
(PLDI), 2020.
[87] T. Norrie and N. Patil, " Google's training chips revealed: TPUv2 and
TPUv3, " in Proc. HotChips, 2020. [Online]. Available: https://hotchips.
org/assets/program/conference/day2/HotChips2020_ML_Training_
Google_Norrie_Patil.v01.pdf.
[88] A. Paszke et al., " PyTorch: An imperative style, high-performance
deep learning library, " in Proc. Adv. Neural Inform. Process. Syst., Curran
Associates, 2019, vol. 32, pp. 8026-8037.
[89] J. Pienaar, " MLIR in TensorFlow ecosystem, " in Proc. Compilers
Mach. Learn. (C4ML), San Diego, 2020.
[90] C. Pilato and F. Ferrandi, " Bambu: A modular framework for the
high level synthesis of memory-intensive applications, " in Proc. Int.
Field Programmable Logic Appl. Conf. (FPL), 2013, pp. 1-4.
[91] C. Ptolemaeus, Ed., System Design, Modeling, and Simulation using
Ptolemy II. Ptolemy.org, 2014.
[92] E Qin et al., " Sigma: A sparse and irregular GEMM accelerator with
flexible interconnects for DNN training, " in Proc. Int. Symp. High Performance
Comput. Architecture (HPCA), 2020, pp. 58-70.
[93] H. Qin, R. Gong, X. Liu, X. Bai, J. Song, and N. Sebe, " Binary neural
networks: A survey, " Pattern Recognit., vol. 105, p. 107,281, 2020. doi:
10.1016/j.patcog.2020.107281.
[94] V. J. Reddi et al., " MLPerf inference benchmark, " 2020, arXiv:1911.02549.
[95] S. Ren, K. He, R. Girshick, and J. Sun, " Faster R-CNN: Towards real-time
object detection with region proposal networks, " IEEE Trans.
Pattern Anal. Mach. Intell., vol. 39, no. 6, pp. 1137-1149, June 2017. doi:
10.1109/TPAMI.2016.2577031.
[96] E. Rijpkema, E. Deprettere, and B. Kienhuis, " Deriving process networks
from nested loop algorithms, " Parallel Process. Lett., vol. 10, no.
02n03, pp. 165-176, June 2000. doi: 10.1142/S0129626400000172.
96
IEEE CIRCUITS AND SYSTEMS MAGAZINE
[97] F. Schuiki, A. Kurth, T. Grosser, and L. Benini, " LLHD: A multi-level
intermediate representation for hardware description languages, "
2020, arXiv:2004.03494.
[98] A. Severance, J. Edwards, H. Omidian, and G. Lemieux, " Soft vector
processors with streaming pipelines, " in Proc. Int. Symp. Field Programmable
Gate Arrays (FPGA), 2014, pp. 117-126.
[99] S. V. Kalluru Srinivas, H. Nair, and V. Vidyasagar, " Hardware aware
neural network architectures using FbNet, " 2019, arXiv:1906.07214.
[100] N. Srivastava, H. Jin, S. Smith, H. Rong, D. Albonesi, and Z. Zhang,
" Tensaurus: A versatile accelerator for mixed sparse-dense tensor computations, "
in Proc. Int. Symp. High Performance Comput. Architecture
(HPCA), 2020, pp. 689-702.
[101] E. Strubell, A. Ganesh, and A. McCallum, " Energy and policy considerations
for deep learning in NLP, " in Proc. Association Comput. Linguistics
(ACL), July 2019, pp. 3645-3650.
[102] I. Swarbrick, D. Gaitonde, S. Ahmad, B. Gaide, and Y. Arbel,
" Network-on-chip programmable platform in VersalTM ACAP architecture, "
in Proc. Int. Symp. Field Programmable Gate Arrays (FPGA), 2019,
pp. 212-221.
[103] M. Tan et al., " MnasNet: Platform-aware neural architecture search
for mobile, " in Proc. IEEE/CVF Conf. Comput. Vision Pattern Recognit. (CVPR),
June 2019.
[104] M. Tan and Q. Le, " EfficientNet: Rethinking model scaling for convolutional
neural networks, " in Proc. Int. Conf. Mach. Learn. (ICML), June
2019, vol. 97, pp. 6105-6114.
[105] H. Tanaka, D. Kunin, D. Yamins, and S. Ganguli, " Pruning neural
networks without any data by iteratively conserving synaptic flow, " in
Proc. 34th Conf. Neural Inform. Process. Syst., 2020.
[106] X. Tang, T. Schneider, S. Kamil, A. Panda, J. Li, and D. Panozzo,
" EGGS: Sparsity-specific code generation, " Comput. Graph. Forum, vol.
39, no. 5, pp. 209-219, Aug. 2020. doi: 10.1111/cgf.14080.
[107] N. Vassilieva, " Characterization and benchmarking of deep learning. "
hpcuserforum.com/presentations/Wisconsin2017/HPDLCook
book4HPCUserForum.pdf
[108] S. I. Venieris, A. Kouris, and C.-S. Bouganis, " Toolflows for mapping
convolutional neural networks on FPGAs: A survey and future directions, "
vol. 51, no. 3, 2018. doi: 10.1145/3186332.
[109] J. Wang, L. Gou, W. Zhang, H. Yang, and H. Shen, " DeepVID: Deep
visual interpretation and diagnosis for image classifiers via knowledge
distillation, " IEEE Trans. Vis. Comput. Graph., vol. 25, no. 6, pp. 2168-
2180, 2019. doi: 10.1109/TVCG.2019.2903943.
[110] J. Yu, C. Eagleston, C. H.-Y. Chou, M. Perreault, and G. Lemieux,
" Vector processing as a soft processor accelerator, " ACM Trans. Reconfigurable
Technol. Syst. (TRETS), vol. 2, no. 2, June 2009. doi: 10.1145/
1534916.1534922.
[111] J. Yu, L. Yang, N. Xu, and T. H. Jianchao Yang, " Slimmable neural
networks, " 2018, arXiv:1812.08928.
[112] O. Zachariadis, N. Satpute, J. Gómez-Luna, and J. Olivares, " Accelerating
sparse matrix-matrix multiplication with GPU tensor cores, "
2020, arXiv:2009.14600.
[113] L. L. Zhang, Y. Yang, Y. Jiang, W. Zhu, and Y. Liu, " Fast hardwareaware
neural architecture search, " 2019, arXiv:1910.11609.
[114] X. Zhang, X. Zhou, M. Lin, and J. Sun, " Shufflenet: An extremely efficient
convolutional neural network for mobile devices, " in Proc. Conf.
Comput. Vision Pattern Recognit. (CVPR), 2018, pp. 6848-6856.
[115] Y. Zhang, R. Zhao, W. Hua, N. Xu, G. Edward Suh, and Z. Zhang,
" Precision gating: Improving neural network efficiency with dynamic
dual-precision activations, " 2020, arXiv:2002.07136.
[116] Z. Zhang and B. Liu, " SDC-based modulo scheduling for pipeline
synthesis, " in Proc. Int. Conf. Comput. Aided Design (ICCAD), 2013,
pp. 211-218.
[117] Z. Zhang, H. Wang, S. Han, and W. J. Dally, " SpArch: Efficient architecture
for sparse matrix multiplication, " 2020, arXiv:2002.08947.
[118] R. Zhao, Y. Hu, J. Dotzel, C. D. Sa, and Z. Zhang. " Building
efficient deep neural networks with unitary group convolutions, " in Proc.
Conf. Comput. Vision Pattern Recognit. (CVPR), 2019, pp. 11,295-11,304.
[119] A. Zhou et al., " Learning N:M fine-grained structured sparse neural
networks from scratch, " 2021, arXiv:2102.04010.
[120] S. Zhou, Y. Wu, Z. Ni, X. Zhou, H. Wen, and Y. Zou, " Dorefa-Net:
Training low bitwidth convolutional neural networks with low bitwidth
gradients, " 2016, arXiv:1606.06160.
[121] C. Zhu, K. Huang, S. Yang, Z. Zhum, H. Zhang, and H. Shen, " An efficient
hardware accelerator for structured sparse convolutional neural
networks on FPGAs, " 2020, arXiv:2001.01955.
SECOND QUARTER 2021
https://old.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02.pdf https://old.hotchips.org/hc31/HC31_1.13_Cerebras.SeanLie.v02.pdf http://hpcuserforum.com/presentations/Wisconsin2017/HPDLCookbook4HPCUserForum.pdf http://hpcuserforum.com/presentations/Wisconsin2017/HPDLCookbook4HPCUserForum.pdf https://hotchips. org/assets/program/conference/day2/HotChips2020_ML_Training_Google_Norrie_Patil.v01.pdf https://hotchips. org/assets/program/conference/day2/HotChips2020_ML_Training_Google_Norrie_Patil.v01.pdf https://hotchips. org/assets/program/conference/day2/HotChips2020_ML_Training_Google_Norrie_Patil.v01.pdf http://www.Ptolemy.org
IEEE Circuits and Systems Magazine - Q2 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2021
