IEEE Circuits and Systems Magazine - Q3 2021 - 1

Circuits
and Systems
IEEE
MAGAZINE
Volume 21, Number 3
Third Quarter 2021
Features
4 Hardware Security Exploiting Post-CMOS
Devices: Fundamental Device Characteristics,
State-of-the-Art Countermeasures,
Challenges and Roadmap
Aditya Japa, Manoj Kumar Majumder, Subhendu K. Sahoo,
Ramesh Vaddi, and Brajesh Kumar Kaushik
Emerging nanoelectronic semiconductor devices have been quite promising in enhancing
hardware-oriented security and trust. However, implementing hardware security primitives
and methodologies requires large area overhead and power consumption. Furthermore,
emerging new attack models and vulnerabilities are regularly evolving and cannot be
adequately addressed by current CMOS technology. This paper for the first time presents
a comprehensive review of numerous post-CMOS technologies based hardware security
primitives and methodologies, particularly true random number generators, physically
unclonable functions, side-channel analysis countermeasures, and hardware obfuscation
techniques. Various beyond-CMOS device technologies including tunneling FET (TFET),
hybrid phase transition FET (HyperFET), carbon nanotube FET (CNTFET), silicon nanowire
FET (SiNWFET), symmetrical tunneling FET (SymFET), phase-change memory (PCM),
spin-transfer torque magnetic tunnel junction (STT-MTJ), resistive random access memory
(RRAM) have been considered in this study. First, the basic principle of operation and
unusual characteristics of nanoelectronic devices used for hardware security applications
have been extensively discussed. Later, CMOS technology challenges and benefits of
emerging nanotechnologies for the design of hardware security primitives and methodologies
have been reported. Finally, different analyses have been presented to demonstrate
the promising performance of post-CMOS devices over the current CMOS technology in
different countermeasures. Additionally, challenges, future directions, and plans have been
presented to achieve more research outcomes in this field.
©SHUTTERSTOCK.COM/SPAINTER_VFX
31 Compute-in-Memory Chips for Deep Learning:
Recent Trends and Prospects
IEEE Circuits and Systems Magazine (ISSN 1531-636X)
(ICDMEN) is published quarterly by the Institute of Electrical
and Electronics Engineers, Inc. Headquarters: 3
Park Avenue, 17th Floor, New York, NY, 10016-5997 USA.
Responsibility for the contents rests upon the authors and
not upon the IEEE, the Society, or its members. IEEE Service
Center (for orders, subscriptions, address changes): 445
Hoes Lane, Piscataway, NJ 08854 USA. Telephone: +1 732
981 0060, +1 800 678 4333. Individual copies: IEEE members
US$20.00 (first copy only), nonmembers US$189 per copy;
US$7.00 per member per year (included in Society fee)
for each member of the IEEE Circuits and Systems Society.
Subscription rates available upon request. Copyright
and Reprint Permission: Abstracting is permitted with
credit to the source. Libraries are permitted to photocopy
beyond the limits of the U.S. Copyright law for private use
of patrons: 1) those post-1977 articles that carry a code
at the bottom of the first page, provided the per-copy fee
indicated in the code is paid through the Copyright Clearance
Center, 222 Rosewood Drive, Danvers, MA 01923; and
2) pre-1978 articles without fee. For other copying, reprint,
or republication permission, write to: Copyrights and
Permissions Department, IEEE Service Center, 445 Hoes
Lane, Piscataway, NJ 08854 USA. Copyright © 2021 by the
Institute of Electrical and Electronics Engineers, Inc. All
rights reserved. Periodicals postage paid at New York, NY,
and at additional mailing offices. Postmaster: Send address
changes to IEEE Circuits and Systems Magazine, IEEE Operations
Center, 445 Hoes Lane, Piscataway, NJ, 08854 USA.
Printed in U.S.A.
Shimeng Yu, Hongwu Jiang, Shanshi Huang, Xiaochen Peng, and Anni Lu
Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall
problem in hardware accelerator design for deep learning. The input vector and weight
matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed
in the analog domain within memory sub-array, leading to significant improvements
in throughput and energy efficiency. Static random access memory (SRAM) and emerging
non-volatile memories such as resistive random access memory (RRAM) are promising
candidates to store the weights of deep neural network (DNN) models. In this review, firstly
we survey the recent progresses in SRAM and RRAM based CIM macros that have been
demonstrated in silicon. Then we discuss general design challenges of the CIM chips
including analog-to-digital conversion (ADC) bottleneck, variations in analog compute,
and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework
that is capable of evaluating versatile device technologies for CIM inference and training
performance from software/hardware co-design's perspective. Lastly we present several
future research directions for CIM such as incremental learning, monolithic 3D integration,
reconfigurable design and potential security vulnerabilities.
57 Thermoelectricity: From History to Modernity
Through the CASS Activity
A.S. Korotkov and V.V. Loboda
October 2020 has become remarkable for commemorating the 140th birthday of the
outstanding academician A.F. Ioffe - " the father of Soviet physics. " A.F. Ioffe supervised
the first research projects on semiconductor physics, in particular, thermoelectricity. In this
article, we introduce the great scientific contributions of A.F. Ioffe and several research
projects of the members of the IEEE CAS Chapter, St. Petersburg, based on the results
of Ioffe's scientific group.
Digital Object Identifier 10.1109/MCAS.2021.3056249
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
1

http://www.SHUTTERSTOCK.COM/SPAINTER_VFX

IEEE Circuits and Systems Magazine - Q3 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2021