IEEE Circuits and Systems Magazine - Q3 2021 - 11

RESET Pulse
Top Electrode
Bit Line
Phase Change Material
Programmable Region
SET Pulse
Heater
Bottom Electrode
(a)
Figure 7. PCM (a) Internal structure (b) Programming pulses.
Word Line
Crystalline Temperature
Room Temperature
Time
(b)
Melting Temperature
states, namely low resistance state (LRS) and high resistance
state (HRS), allowing to store a logic 1 or 0 as
shown in Fig. 8(b). The conduction through the RRAM
is primarily due to the trap-assisted-tunneling that is
the transportation of electrons in the oxygen vacancies
[50]. The process of setting the resistance of RRAM to
LRS is called as SET process and setting the resistance
of RRAM to HRS is called a RESET process. Thus the
RRAM varies its resistance and works as a non-volatile
memory element
RRAM exhibits cycle to cycle variations in HRS and
LRS due to the oxide breakdown and re-oxidation.
These variations in resistance are obtained from the
defects of oxide material and result in Gaussian distribution.
As conduction in RRAM is due to the trapassisted-tunneling,
the current through RRAM exhibits
stochastic variations with time [70]. The variation in
current through the RRAM results in random telegraph
noise (RTN) [71]. The resistance levels of RRAM are
subject to high RTN that lead to large READ current
noises. These RTN signals of RRAM are much larger
than the conventional MOSFET. The generation of cycleto-cycle
variations and RTN allows the emerging RRAM
to be a more appropriate entropy source for PUF and
TRNG design [70], [72]. Besides, RRAM write-time variability
and ultra-low power consumption characteristics
have also been explored for low-power overhead
DPA countermeasure [73].
F. STT-MTJ Stochastic Switching Behavior
The spin-transfer torque magnetic tunnel junction
(STT-MTJ) has attracted wide attention due to its great
potential to build the next generation of non-volatile
THIRD QUARTER 2021
memory [47]. Compared to existing memory technologies,
STT-MTJ based magnetic random-access memory
(MRAM) shows low power consumption, high-speed
operation, infinite endurance, high density, and compatibility
with standard CMOS process memories [51].
It works on the principle of tunnel magneto-resistance
and stores the data in the form of the resistance state
of MTJ. It is designed using one ferromagnetic free
layer, ferromagnetic fixed layer, and tunnel barrier. Figure
9(a) shows the general structure of STT-MTJ wherein
two ferromagnetic layers are separated by the tunnel
barrier. Generally, the tunnel barrier used in MTJs is
oxide material like MgO, TiO,
XX and AIO.X
The electrical
resistance of the MTJ device depends on the relative
Top Electrode
LRS
Metal Oxide
VReset
HRS
Bottom Electrode
(a)
(b)
Figure 8. RRAM (a) Typical device architecture (b) V-I characteristics
representing different RRAM states.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
11
Voltage
VSet
PCM
Magnitude
Current
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