IEEE Circuits and Systems Magazine - Q3 2021 - 14

exhibits degradation in performance with low reliability,
low uniqueness, and high bit error rate [91]. Theoretically,
PUFs are unclonable, but there exist several attacks
and methodologies to clone a PUF circuit and obtain its
challenge-response pairs [92]. A PUF generates a digital
response upon applying a challenge as shown in Fig.
12(a). The response of the PUF is determined by complex
function and that is unique to each PUF device [92]. PUFs
with identical manufacturing processes generate a different
set of keys due to the physical variations that exist
between devices as shown in Fig. 12(b). PUFs have been
explored in several security applications including chip
identification and authentication, secure key generation
for lightweight encryption, hardware piracy and chip
counterfeiting, hardware metering, and protection of intellectual
property [93]-[95]. Historically, various CMOS
based PUF designs have been demonstrated and used
in divergent applications. With the wide variety of PUFs
based on different entropy sources, circuit topologies,
and architectures, it is difficult to categorize them. However,
depending on the size of challenge-response pairs
(CRPs), these are classified as weak PUFs and strong
PUFs [96]. Strong PUFs consist of the large number of
CRPs wherein the number of CRPs increases exponentially
with PUF cells. Contrary to this, weak PUF CRPs
increase linearly with number of PUF cells. Strong PUFs
include arbiter PUFs and ring oscillator based PUFs that
works on the delay difference of two identical paths [96]-
[97]. The Arbiter PUF determines the faster path out of
two identical delay paths by applying a race signal [98].
Even though the two paths are identical, the delay difference
is obtained by using process variations. Several
arbiter PUFs have been proposed which are lightweight
but are highly vulnerable to modeling attacks. The ring
80
60
40
20
(88)
(29)
500
1,000
Area (µm2)
(a)
80
(78)
CMOS
60
(81)
40
20
(30)
(29,60,84-85)
050
(47,87)
100
Bitrate (Mb/s)
(c)
Figure 11. Comparison of emerging technologies based TRNGs (a) bit-energy consumption against the area (b) bitrate against
area (c) bit-energy consumption against bitrate.
14
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
(74)
(88)
150
(47)
200
(79)
(28)
(77)
High Speed With
Low Energy Consumption
Spintronic Devices
RRAM
TFET
(74)
(30)
(81)
1,500
2,000
40
(78)
160
200
(86)
More Efficient
(79)
(28)
120
80
(47)
(88)
(84)
(87)
(60)
(74)
Faster and Smaller
(78)
(29)
(28, 30)
(30)
1,000
2,000
Area (µm2)
(b)
3,000
(77)
4,000
(47,87-88)
Energy Consumption (pJ/bit)
Energy Consumption (pJ/bit)
Bitrate (Mb/s)

IEEE Circuits and Systems Magazine - Q3 2021

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