IEEE Circuits and Systems Magazine - Q3 2021 - 15

oscillator based PUF explores the frequency difference
obtained by the process variations in identical ring oscillator
designs [99]. Although the arbiter PUFs are lightweight,
ring oscillator based PUFs have attracted wide
attention due to their fabrication simplicity and security
compared to other PUFs. However, the response of RO
PUF is highly vulnerable to temperature variation, power
supply noise, and aging.
On the other hand, weak PUF are memory based
PUFs that exploit metastable states of cross-coupled
inverters [100]. Memory-based PUFs are particularly
attractive compared to other PUF designs since they
require minimal hardware components [101]. These
memory-based PUFs were widely designed using CMOS
based static random access memory (SRAM) and dynamic
random access memory (DRAM) [101]-[102].
SRAM based PUF is one of the most thoroughly studied
designs that evaluate the power-up pattern like a fingerprint
of the device. However, SRAM based PUFs occupy
a large area and exhibit unreliability. Moreover,
the SRAM based PUFs can be physically closable and
highly vulnerable to fault injection attacks. An Alternative
to SRAM, DRAM PUFs have also been demonstrated
that explore random initialization of capacitor
values in DRAM cell at startup time [103]. While DRAM
PUF shows a higher density than SRAM PUF, but they
exhibit lower stability.
There exist another class of PUF devices that exhibit
the ability to change its response to the same challenge
[96]. These are named reconfigurable PUFs (RPUF) and
such PUFs are required for the number of applications
including updating the secret key of cryptographic devices
and communication protocols. The RPUFs are
further classified into logically RPUF (L-RPUF) and
physically (P-RPUF) [55]. The L-RPUF explores control
logic to generate different challenge-response pairs.
On the other hand, P-RPUF utilizes intrinsic physical
properties, achieves lower area overhead with enhanced
security. Several RPUFs have been proposed in
the literature to enhance the security and reliability of
conventional PUFs [55], [96]. The challenges of CMOS
based PUFs are listed below.
■ CMOS based PUF designs demonstrate two major
issues that are the high bit error rate (BER) and
PUF
Challenge
(C1;C2....;Cx)
(a)
PUF1
Challenge
(C)
PUF2
Challenge
(C)
Challenge
(C)
PUF3
Response
(R3)
Response
(R2)
Response
(R1)
Response
(R1;R2....;Rx)
Challenge
(C)
PUFx
Response
(Rx)
(b)
Figure 12. Block diagram of PUF (a) Generates different
responses for a given challenge (b) Generates different responses
for different PUF designs upon applying the same
challenge.
Table 1.
Energy consumption and area comparison of post-CMOS devices based PUF designs.
Device
PCM [55]
CNTFET [64]-[65]
STT-MTJ [75], [106]
RRAM [72], [108]
THIRD QUARTER 2021
Characteristics
Process variations and programming uncertainties of
PCM cells
Sensitivity to strong process variations
Variations in chirality, diameter, and doping
concentration of CNT
Stochastic switching behavior
Stochastic switching and variability in resistance
Energy consumption
(pJ/bit)
8.49
0.049
0.67×10-3
0.001
24
9.59
9.88
Area (µm2)
-
1.87
-
2
189
8.3
-
IEEE CIRCUITS AND SYSTEMS MAGAZINE
15
IEEE Circuits and Systems Magazine - Q3 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2021
