IEEE Circuits and Systems Magazine - Q3 2021 - 18

shows an overview of different side-channel attacks
considering various physical phenomena like power,
electromagnetic, and photonic information of IC/crypto
engine.
i. Differential Power Analysis Countermeasures
Differential analysis has become a popular attacking
method since the power information of cryptographic
engines is easily obtained [114]. DPA measures and
process the power supply current of cryptographic device
to obtain the secret key information. DPA extremely
successful on CMOS based crypto circuits since
dynamic power consumption in these logic circuits
is highly dependent on the data being processed. To
protect the CMOS based crypto engines against DPA,
several countermeasures have been demonstrated.
These countermeasures can be categorized into two
levels namely architectural and logic level. Balanced
logic-based countermeasures including sense amplifier
logic (SABL), randomized multi-topology logic
(RMTL), homogeneous dual-rail logic (HDRL), secure
positive feedback adiabatic logic, FinFET based secure
adiabatic logic (FinSAL), and differential symmetric
pull-down network gates provide an excellent DPA
resilience but often require extensive design efforts,
exhibited higher delay, and area overhead [34]-[37].
Another technique that exploits fully integrated onchip
voltage regulators is demonstrated to protect
RRAM
Variability
in
STT-MTJ
Uniform
Power
Consumption
DPA
Countermeasure
p-i-n
Low
Leakage
CNTFET
Hysterises
on
Transition
HyperFET
Figure 14. Emerging devices and characteristics used for
DPA countermeasures.
18
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Forward
Current and Low
Subthreshold
Swing
TFET
Write-Time
SymFET
Drain
Current for
Narrow-Band
Voltages
crypto engines from DPA [114]. Integrated all-digital
low dropout voltage regulator (ADLDO) is also proposed
to enhance the DPA resilience [115]. Integrating
CMOS RNG with crypto devices is proposed to decorrelate
the power and processed data [116]. However,
CMOS based RNG designs exhibited high area power
and performance trade-offs with technology scaling
[78]-[79]. The challenges of CMOS based DPA countermeasures
are listed below.
■ Traditionally, CMOS devices show high leakage at
lower channel lengths. Due to this, CMOS based
systems are highly vulnerable to DPA attacks.
■ Major CMOS based cryptographic designs/architectures
explore conventional CMOS logic topologies
that is highly vulnerable to DPA.
■ The DPA attack on CMOS based systems explores
a hamming weight or distance model that is well
known and easily accessible.
■ Moreover, CMOS based DPA countermeasures
result in increased power dissipation, area overhead,
and complexity.
Orthogonal to current CMOS based countermeasures,
beyond-CMOS device technologies have been utilized
to reduce area overheads while obtaining a similar level
of DPA resilience. Figure 14 shows the reported emerging
devices and their peculiar electrical characteristics
that are utilized to design DPA resilient systems. A Resistive
random access memory exhibits unique characteristics
such as variability in write time, ultra-low
power consumption, and high density to counter DPA
attacks. An inverse RRAM based DPA countermeasure is
proposed that achieves 80% lower power compared to
equivalent CMOS countermeasure [73]. A power analysis
resilient circuit methodology is also demonstrated
by using the asymmetric resistive states and switching
behavior of the STT-MTJ device that exhibited minimum
area and power overhead in [76]. A novel MTJ based
lookup table method is introduced to design low energy
and DPA resistant embedded cryptographic hardware
[117]. A CNTFET as a promising alternative to CMOS has
proved to enhance the power analysis resilience [66].
This work demonstrated that CNTFET based cipher exhibits
a lower success rate and lower correlation coefficient
difference of correct key and closest wrong key
guess compared to CMOS cipher. HyperFET devices
have been shown as new paradigms for enhancing security
against power analysis attacks. The DPA on HyperFET
based substitution box of PRIDE revealed a 25 times
security enhancement compared to the conventional
designs [56]. Recently, the TFET device is explored for
DPA resilient circuit design utilizing the unique device
characteristics. TFET based symmetric pass gate adiabatic
logic is introduced that achieves 62% power saving
THIRD QUARTER 2021
IEEE Circuits and Systems Magazine - Q3 2021

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