IEEE Circuits and Systems Magazine - Q3 2021 - 21

suffer from a huge loss of revenue due to these hardware
security breaches [38]. Hardware obfuscation that
hides the original functionality of design has become
one of the most popular IC protection techniques [39].
As the process of producing an IC consists of three major
levels: design, manufacturing, and testing, the hardware
obfuscation techniques have been proposed mainly
at the design and manufacturing level. Design level
hardware obfuscation techniques can be performed in
two ways: structural obfuscation and physical design
obfuscation [40]. Structural obfuscation hides the original
functionality of the circuit/system by using the randomized
placement of logic, routing, and dummy wires
[41]. Several MOS based structural obfuscation techniques
such as logic encryption, PUF based key generation
for obfuscated cells, multi-key based techniques,
and cyclic logic obfuscation have been proposed that
achieve low power and high area overheads [133]-
[135]. However, structural obfuscation cannot prevent
recovering gate netlist completely. If the adversary acquires
enough time and resources, one can succeed in
delayering of IC and gets circuit functionality. On the
other hand, physical design obfuscation that exploits
stealthy manipulations such as changes in doping concentrations,
dielectric manipulation, and material compositions
has attracted wide attention due to difficulty
in extracting the gate netlist [133]. Several MOS based
physical design obfuscation techniques like source or
drain doping changes at the device level, gate camouflaging,
and logic level countermeasures have been
proposed [136]-[137].
Split manufacturing is another major technique to
overcome threats in the semiconductor supply chain
[138]. Split manufacturing divides the circuit into two
layers that are front end of line (FEOL) and back end
of line (BEOL). These layers are fabricated in different
Table 5.
Comparison of different side-channel attacks.
Parameter
Physical phenomenon used
Direct access of IC/system
Computation data required
Depth of the attack
Possibility of detection
Emerging devices/materials
explored to mitigate
foundries, an untrusted foundry manufactures FEOL
layer and shifts that to the trusted foundry to perform
BEOL fabrication [138]. This approach hides the IC BEOL
information from untrusted foundry which prevents
several security issues [139]. FEOL consists of MOS transistors
and many complex routing layers, thus a highend
foundry (untrusted) performs its fabrication [139].
Besides, IC fabrication can be completed by a low-end
foundry (trusted) with remaining less BEOL routing connections.
Exploring split manufacturing, several IC designs
have been implemented successfully with the low
area and performance overhead [138]-[139]. Recently,
split manufacturing is applied to 3D IC designs where
each tire can be fabricated in a separate foundry [140].
However, split manufacturing shows several design challenges
[141]. There must be high compatibility between
technologies used for FEOL and BEOL. Apart from this,
a random selection of split may affect the existing IP
designs. Moreover, it is identified that attacks on FEOL
can effectively reveal the BEOL connection information.
Thus, CMOS based hardware obfuscation techniques
shown several challenges which are listed below:
■ Conventional CMOS device properties and design
rules of fabricated ICs are easily accessible that
makes the attacker's effort easier in delayering
the IC [133].
■ CMOS device characteristics are deterministic
and architectures used for systems design are
much more conventional. This behavior is highly
undesirable for hardware obfuscation applications.
■
CMOS based hardware obfuscation techniques
exhibit higher power consumption and area overheads.
In
contrast to MOS based techniques, various beyond-CMOS
devices have been explored that achieve a
Power analysis attack
Power consumption
information
Required[113]
High[123]
Possible on complete
hardware[113]
Higher[115]
TFET[62], HyperFET[56],
CNTFET[66], STT-MTJ[117],
RRAM[73]
EM analysis attack
Electromagnetic signal
Not Required[122]
Relatively low[123]
Can reach specific part
of hardware[121]
Lower[122]
Limited*
*To the best of authors knowledge none of works have demonstrated in the literature
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
21
Photon analysis attack
Photonic emission
Required[127]
Relatively low[126]
Can reach single transistor
[127]
Higher[127]
Spintronic based GSHE
device[129], graphene and
carbon nanotube [130]-[131]
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