IEEE Circuits and Systems Magazine - Q3 2021 - 22

higher level of security for hardware obfuscation while
maintaining minimum power and area overheads. SiNWFET
and TFET based low-cost polymorphic logic gates
have been demonstrated by utilizing the tunable polarity
characteristics for IP piracy prevention, IP protection,
and to mitigate hardware trojan attacks [58]. Moreover,
SiNWFET based camouflaging layout uses a relatively
lower area and hampers the ability of reverse engineering.
A novel circuit obfuscation technique is proposed
exploiting spin-orbit torque MTJ based look-up-tables
as reconfigurable logic where it is impossible to apply
reverse engineering even by using scanning electron
microscopy (SEM) and transmission electron microscopy
(TEM) techniques [142]. Utilizing the concept of
variation in magnetization direction, an all-spin logic
device (ASLD) provided a novel opportunity to change
the functionality of the circuit with the same structure
[143]. Recently, a new hardware-secure circuit design
methodology has been demonstrated wherein the TFET
based flip-flops were obfuscated exploring TFET p-i-n
forward current [61]. The unique characteristics like
amorphous resistance of PCM are used to check whether
a PCM cell is " fresh " or tampered without any extra
cost. A newly manufactured PCM in the crystalline phase
shows higher resistance than the amorphous resistance
of a reset PCM cell [69]. The innate polymorphism and
tunable stochastic behavior of the giant spin hall effect
(GSHE) switch is leveraged to enable IP protection (by
means of logic locking and camouflaging) [144]. Table 6
summarizes the post-CMOS technologies based hardware
obfuscation works wherein the benefits of these
techniques over CMOS counterparts have been listed. It
can be observed that the emerging hardware obfuscation
techniques provide several advantages over CMOS
based obfuscation. While STT-MTJ based circuit obfuscation
achieves high resilience towards SEM or TEM and
TFET device based obfuscation utilizing p-i-n forward
current exhibits high robustness towards RE attacks.
IV. Emerging Devices for Hardware
Security: Challenges and Roadmap
The discussion of this paper mainly focuses on the various
emerging device characteristics based hardware security
primitives and methodologies. However, exploiting
these devices for hardware security applications
create several challenges. This section presents several
challenges and future plans to enhance the outcomes
of beyond-CMOS devices based hardware security.
Further, the summary of beyond-CMOS device based
hardware security countermeasures has been demonstrated.
The notable challenges faced by researchers in
this domain have been listed below:
A. Challenges
■ Emerging device architectures that demonstrate
excellent security features show high power and
energy consumption. For example, STT-MTJ devices
demonstrate excellent security-oriented features
but show higher write energy consumption.
■ The limited availability of novel circuits and system
architectures that efficiently extract security
benefits.
■ Lack of security-specific device models that are highly
compact in size and accurate for circuit design.
■ Security characteristics of post-CMOS devices are
not well studied and metrics for hardware security
assessment are not well established. For example,
NCFET shows hysteresis (as HyperFET) and
Table 6.
Post-CMOS technologies based hardware obfuscation techniques.
Device
SiNWFETs [58]
STT-MTJ [142]
ASL device [143]
TFET[58], [61]
PCM [69]
GSHE [144]
22
Characteristics
Tunable polarity
Magnetization states
Changing magnetization
direction
p-i-n forward
characteristics
Tunable polarity
Variation in cell
resistance
Forming step
tunable stochastic
behavior
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Technique
Camouflaging layout
Circuit obfuscation
Logic locking
Device based
obfuscation
Logic locking
Device level tamper
resistance
IP protection
Result Comparing with CMOS
* 3× low area
* 6× key enlargement
* 10% low area
* High resilience towards SEM or TEM
-
* Highly Robust to RE attacks
* Low power and compact polymorphic
logic gates
* Resilience towards SEM
* Tamper detection without any
extra circuitry
* Robust against boolean satisfiability
(SAT) attacks
THIRD QUARTER 2021
IEEE Circuits and Systems Magazine - Q3 2021

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