IEEE Circuits and Systems Magazine - Q3 2021 - 24

Current CMOS technology scaling and emerging new security attacks
made the existing hardware security methodologies inadequate.
must exhibit security-oriented characteristics. To have
a fair assessment of beyond-CMOS device-based circuits,
the device model needs to be accurate. Additionally,
the device models need to run several times
to collect large data for testing of hardware security
primitives/methodologies. For example, side-channel
analysis countermeasures require thousands of power
traces that need the device model to run several times
[62]. Thus, the device model used for hardware security
applications need to be compact to acquire lesser
simulation time.
The existing device models do not necessarily incorporate
device variabilities, stochastic processes, and
security-oriented unique features. For example, several
TFET based works have demonstrated energy-efficient
circuit design by exploring Verilog models [43], [57].
However, the TFET Verilog models available in the research
community doesn't capture the device variabilities
that can be used for PUF design [57], [62]. On the
other hand, hyperFET devices utilize a phase transition
material and achieve steep switching characteristics
[56]. Research work focused on hyperFET used a
Verilog model by integrating individual phase change
material and FinFET models in SPICE to perform the
hyperFET based circuit analysis [56]. This is because
there are no unified and globally available hyperFET
models in the research community. Additionally, several
hyperFET based works have focused on low-power
digital logic applications and few works have used them
for security applications [42], [48]. Therefore, compact
and accurate device models that show several securityoriented
characteristics are required to obtain excellent
outcomes in this field.
V. Summary and Discussion of Emerging
Devices Based Countermeasures
Through the extensive review and analysis, we could
identify that post-CMOS devices based hardware security
countermeasures achieve remarkable benefits
over existing CMOS designs. Table 7 shows the summary
of emerging device candidates that are explored
to demonstrate various hardware security countermeasures.
These devices have demonstrated several
unusual characteristics including p-i-n forward leakage,
ambipolarity, stochastic variation in switching,
bell-shaped I-V characteristics, strong process variations,
threshold dispersion, etc. Exploiting these characteristics,
several countermeasures have been de24
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CIRCUITS AND SYSTEMS MAGAZINE
signed for hardware security applications. Specifically,
this review has considered four different hardware
security primitives/methodologies such as TRNG, PUF,
SCA countermeasures, and hardware obfuscation.
It
can be observed that the memory devices including
RRAM and STT-MTJ have been explored to design several
hardware security countermeasures due to their
excellent security-oriented device characteristics. On
the other hand, numerous hardware security techniques
leveraged steep switching TFET with various
unique characteristics and exhibited several benefits.
Apart from this, these devices still show several challenges
including low ON-current, lower transition time,
high leakage, high programming current, etc. Although
various
advanced-CMOS device/circuit
level
techniques
and methodologies have been adopted to mitigate
these challenges, they cannot be fully eliminated.
These challenges become a bottleneck to the semiconductor
industry that makes the beyond-CMOS devices
based hardware security techniques unpopular.
Table 8 presents the performance comparison of
emerging devices for different hardware security countermeasures.
STT-MTJ with its intrinsic stochastic
switching behavior has become a highly suitable device
for TRNG design. STT-MTJ based TRNG designs
obtained lower area and energy consumption compared
to the other designs. Apart from this, RRAM
based PUF design exhibited super reliability (proved
to be highly reliable) compared to other designs due
to the variations in resistance. However, the RRAM
based PUF designs have demonstrated relatively more
area and energy consumption compared to the CMOS
designs. Further, STT-MTJ based designs proved to be
side-channel secure by achieving higher MTD. Nevertheless,
STT-MTJ based logic designs/applications exhibited
large energy consumption due to the high write
current requirement of the device. Post-CMOS devices
have achieved several benefits and have also shown
unavoidable challenges. Therefore, immediate research
effort is required in this field to satisfy the present and
future needs of hardware security.
VI. Conclusion
Current CMOS technology scaling and emerging new
security attacks made the existing hardware security
methodologies inadequate. Beyond-CMOS devices
have manifested new opportunities and higher-order
security benefits due to their superior characteristics.
THIRD QUARTER 2021
IEEE Circuits and Systems Magazine - Q3 2021

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