IEEE Circuits and Systems Magazine - Q3 2021 - 27

committees constituted by government and non-government
organizations. He is currently serving as Distinguished
Lecturer (DL) of IEEE Electron Devices Society
(EDS) to offer EDS Chapters with quality lectures in
his research domain. He is an Editor of IEEE Transactions
on Electron Devices; Associate Editor of IET Circuits,
Devices & Systems; Editor of Microelectronics Journal,
Elsevier; Editorial Board member of Journal of
Engineering, Design and Technology, Emerald and Circuit
World, Emerald. He has received many awards and recognition
from the International Biographical Center
(IBC), Cambridge. He has 12 books to his credit published
by reputed publishers such as CRC Press, Springer,
Artech and Elsevier. One his books, titled " Nanoscale
Devices: Physics, Modeling, and Their Application " , CRC
Press won 2018 Outstanding Book and Digital Product
Awards in the Reference/Monograph Category from Taylor
and Francis Group. He has been offered with fellowships
and awards from DAAD, Shastri Indo Canadian Institute
(SICI), ASEM Duo, United States-India Educational
Foundation (Fulbright-Nehru Academic and Professional
Excellence). His research interests are in the areas of
high-speed interconnects, carbon nanotube-based designs,
organic electronics, device circuit co-design, optics
& photonics based devices, image processing, spintronics-based
devices, circuits and computing.
References
[1] F. Li, A. Shinde, Y. Shi, J. Ye, X. Y.Li, and W. Z. Song, " System statistics
learning-based IoT security: Feasibility and suitability, " IEEE
J. Internet Things, vol. 6, no. 4, pp. 6396-6403, Aug. 2019. doi: 10.1109/
JIOT.2019.2897063.
[2] Y.S. Dabbagh and W. Saad, " Authentication of wireless devices in the
Internet of Things: Learning and environmental effects, " IEEE J. Internet
Things, vol. 6, no. 4, pp. 6692-6705, Aug. 2019. doi: 10.1109/JIOT.2019.2910233.
[3] A. Chattopadhyay, A. Ukil, D. Jap and S. Bhasin, " Toward threat of
implementation attacks on substation security: Case study on fault detection
and isolation, " IEEE Trans. Ind. Informat., vol. 14, no. 6, pp. 2442-
2451, June 2018. doi: 10.1109/TII.2017.2770096.
[4] S. Ghosh, " Spintronics and security: Prospects, vulnerabilities, attack
models, and preventions, " Proc. IEEE, vol. 104, no. 10, pp. 1864-
1893, Oct. 2016. doi: 10.1109/JPROC.2016.2583419.
[5] S. Kannan, N. Karimi, O. Sinanoglu, and R. Karri, " Security vulnerabilities
of emerging nonvolatile main memories and countermeasures, "
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 34, no. 1, pp.
2-15, Jan. 2015. doi: 10.1109/TCAD.2014.2369741.
[6] " The cost of malicious cyber activity to the US economy, " White House,
2018. [Online]. Available: https://www.whitehouse.gov/wp-content/
uploads/2018/03/The-Cost- of -Mal icious-Cyber-Act ivity- to - the
-U.S.-Economy.pdf
[7] M. Chen, E. Moghaddam, N. Mukherjee, J. Rajski, J. Tyszer, and J.
Zawada, " Hardware protection via logic locking test points, " IEEE Trans.
Comput.-Aided Design Integr. Circuits Syst., vol. 37, no. 12, pp. 3020-3030,
Dec. 2018. doi: 10.1109/TCAD.2018.2801240.
[8] S. Roshanisefat, H. M. Kamali, H. Homayoun, and A. Sasan, " SAThard
cyclic logic obfuscation for protecting the IP in the manufacturing
supply chain, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 28,
no. 4, pp. 954-967, Apr. 2020. doi: 10.1109/TVLSI.2020.2968552.
[9] R. Spreitzer, V. Moonsamy, T. Korak, and S. Mangard, " Systematic
classification of side-channel attacks: A case study for mobile devices, "
IEEE Commun. Surveys Tuts., vol. 20, no. 1, pp. 465-488, Firstquarter
2018. doi: 10.1109/COMST.2017.2779824.
THIRD QUARTER 2021
[10] S. Bhunia, M. S. Hsiao, M. Banga, and S. Narasimhan, " Hardware
trojan attacks: Threat analysis and countermeasures, " Proc. IEEE, vol.
102, no. 8, pp. 1229-1247, Aug. 2014. doi: 10.1109/JPROC.2014.2334493.
[11] X. Wang, Y. Han, and M. Tehranipoor, " System-level counterfeit detection
using on-chip ring oscillator array, " IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 27, no. 12, pp. 2884-2896, Dec. 2019. doi: 10.1109/
TVLSI.2019.2930532.
[12] H. Kumar, T. Jabbari, G. Krylov, K. Basu, E. G. Friedman, and R.
Karri, " Toward increasing the difficulty of reverse engineering of RSFQ
circuits, " IEEE Trans. Appl. Supercond., vol. 30, no. 3, pp. 1-13, Apr. 2019.
doi: 10.1109/TASC.2019.2901895.
[13] M. Fyrbiak et al., " HAL-The missing piece of the puzzle for hardware
reverse engineering, trojan detection and insertion, " IEEE Trans.
Dependable Secure Comput., vol. 16, no. 3, pp. 498-510, June 2019. doi:
10.1109/TDSC.2018.2812183.
[14] T. Moos, A. Moradi, and B. Richter, " Static power side-channel
analysis-an investigation of measurement factors, " IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 28, no. 2, pp. 376-389, Feb. 2020. doi:
10.1109/TVLSI.2019.2948141.
[15] P. De, C. Mandal, and U. Prampalli, " Path-balanced logic design to
realize block ciphers resistant to power and timing attacks, " IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 5, pp. 1080-1092, May
2019. doi: 10.1109/TVLSI.2019.2896377.
[16] S. Verbauwhede et al., " EM information security threats against
RO-based TRNGs: The frequency injection attack based on IEMI and EM
information leakage, " IEEE Trans. Electromagn. Compat., vol. 61, no. 4,
pp. 1122-1128, Aug. 2019.
[17] W. Wang, Y. Yu, F. X. Standaert, J. Liu, Z. Guo, and D. Gu, " Ridgebased
DPA: improvement of differential power analysis for nanoscale
chips " , IEEE Trans. Inf. Forensics Security, vol. 13, no. 5, pp. 1301-1316,
May 2018. doi: 10.1109/TIFS.2017.2787985.
[18] S. U. Hussain, M. Majzoobi, and F. Koushanfar, " A built-in-self-test
scheme for online evaluation of physical unclonable functions and
true random number generators, " IEEE Trans. Multi-Scale Comput. Syst.,
vol. 2, no. 1, pp. 2-16, Mar. 2016. doi: 10.1109/TMSCS.2016.2519902.
[19] W. Shan, S. Zhang, J. Xu, M. Lu, L. Shi, and J. Yang, " Machine learning
assisted side-channel-attack countermeasure and its application on
a 28-nm AES circuit, " IEEE J. Solid-State Circuits, vol. 55, no. 3, pp. 794-
804, Mar. 2020. doi: 10.1109/JSSC.2019.2953855.
[20] S. Koteshwara, C. H. Kim, and K. K. Parhi, " Key-based dynamic
functional obfuscation of integrated circuits using sequentially triggered
mode-based design, " IEEE Trans. Inf. Forensics Security, vol. 13,
no. 1, pp.79-93, Jan. 2018. doi: 10.1109/TIFS.2017.2738600.
[21] C. H. Chang, Y. Zheng, and L. Zhang, " A retrospective and a look
forward: Fifteen Years of physical unclonable function advancement, "
IEEE Circuits Syst. Mag., vol. 17, no. 3, pp. 32-62, Thirdquarter 2017. doi:
10.1109/MCAS.2017.2713305.
[22] A. Diaz-Perez and J. J. Garza-Saldana, " Key establishment protocol
for a patient monitoring system based on PUF and PKG, " in Proc. IEEE
Int. Conf. Emerg. Technol. Smarter World, Melville, 2013, pp. 1-6.
[23] M. H. Mahalat, S. Saha, A. Mondal, and B. Sen, " A PUF based light weight
protocol for secure WiFi authentication of IoT DEVICES, " in Proc. IEEE Int.
Symp. Embedded Comput. Syst. Design, Cochin, India, 2018, pp. 183-187.
[24] V. R. Pamula, X. Sun, S. M. Kim, F. Rahman, B. Zhang, and V. S. Sathe,
" A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit highly digital true-randomnumber
generator with integrated de-correlation and bias correction, "
IEEE Solid-State Circuits Lett., vol. 1, no. 12, pp. 237-240, Dec. 2018. doi:
10.1109/LSSC.2019.2896777.
[25] Y. Wen and W. Yu, " Machine learning-resistant pseudo-random
number generator, " IET Electron. Lett., vol. 55, no. 9, pp. 515-517, May
2019. doi: 10.1049/el.2019.0485.
[26] S. K. Satpathy et al., " An all-digital unified physically unclonable
function and true random number generator featuring self-calibrating
hierarchical von Neumann extraction in 14-nm tri-gate CMOS, " IEEE J.
Solid-State Circuits, vol. 54, no. 4, pp. 1074-1085, Apr. 2019. doi: 10.1109/
JSSC.2018.2886350.
[27] D. Liu, Z. Liu, L. Li, and X. Zou, " A low-cost low-power ring oscillator-based
truly random number generator for encryption on smart
cards, " IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 6, pp. 608-612,
June 2016. doi: 10.1109/TCSII.2016.2530800.
[28] K. Yang, D. Blaauw, and D. Sylvester, " An all-digital edge racing true
random number generator robust against PVT variations, " IEEE J. SolidState
Circuits, vol. 51, no. 4, pp. 1022-1031, Apr. 2016.
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IEEE Circuits and Systems Magazine - Q3 2021

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