IEEE Circuits and Systems Magazine - Q3 2021 - 29

change material, " in Proc. IEEE Int. Carnahan Conf. Security Technology,
Rome, 2014, pp. 1-6.
[69] N. Noor, R. S. Khan, S. Muneer, and H. Silva, " Tamper evidence of
SEM imaging attack in phase change memory nanodevices, " in Proc.
IEEE Int. Conf. Nanotechnol., Macao, 2019, pp. 400-404.
[70] Y. Pang et al., " Optimization of RRAM-based physical unclonable
function with a novel differential read-out method, " IEEE Electron Device
Lett., vol. 38, no. 2, pp. 168-171, Feb. 2017. doi: 10.1109/LED.2016.2647230.
[71] F. M. Puglisi, N. Zagni, L. Larcher, and P. Pavan, " Random telegraph
noise in resistive random access memories: Compact modeling and
advanced circuit design " , IEEE Trans. Electron Devices, vol. 65, no. 7,
pp. 2964-2972, July 2018. doi: 10.1109/TED.2018.2833208.
[72] R. Liu, H. Wu, Y. Pang, H. Qian, and S. Yu, " Extending 1kb RRAM array
from weak PUF to strong PUF by employment of SHA module, " in Proc. IEEE
Int. Symp. Hardware-Oriented Security Trust, Beijing, 2017, pp. 67-72.
[73] G. Khedkar, D. Kudithipudi, and G. S. Rose, " Power profile obfuscation
using nanoscale memristive devices to counter DPA attacks, " IEEE
Trans. Nanotechnol., vol. 14, no. 1, pp. 26-35, Oct. 2014. doi: 10.1109/
TNANO.2014.2362416.
[74] B. Perach, " An asynchronous and low-power true random number generator
using STT-MTJ, " IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.
27, no. 11, pp. 2473-2484, Nov. 2019. doi: 10.1109/TVLSI.2019.2927816.
[75] A. Kumar, S. Sahay and M. Suri, " Switching-time dependent PUF using
STT-MRAM, " in Proc. IEEE Int. Conf. VLSI Design Int. Conf. Embedded
Syst., Pune, 2018, pp. 434-438.
[76] S. B. Dodo, R. Bishnoi, and M. B. Tahoori, " Secure STT-MRAM bitcell
design resilient to differential power analysis attacks, " IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 28, no. 1, pp. 263-272, Oct. 2019.
doi: 10.1109/TVLSI.2019.2940449.
[77] I. Cicek, A. E. Pusane, and G. Dundar, " An integrated dual entropy core
true random number generator, " IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.
64, no. 3, pp. 329-333, Mar. 2017. doi: 10.1109/TCSII.2016.2568181.
[78] K. Yang, D. Fick, M. B. Henry, Y. Lee, D. Blaauw, and D. Sylvester,
" A 23Mb/s 23pJ/b fully synthesized true-random-number generator in
28nm and 65nm CMOS, " in IEEE Int. Solid-State Circuits Conf. Dig. Tech.
Papers, San Francisco, CA, 2014, pp. 280-281.
[79] E. Kim, M. Lee, and J. J. Kim, " 8.2 8Mb/s 28Mb/mJ robust true-random-number
generator in 65nm CMOS based on differential ring oscillator
with feedback resistors, " in IEEE Int. Solid-State Circuits Conf. Dig.
Tech. Papers, San Francisco, 2017, pp. 144-145.
[80] V. B. Suresh, and W. P. Burleson, " Entropy and energy bounds for
metastability based TRNG with lightweight post-processing, " IEEE
Trans. Circuits Syst. I, Regular Papers, vol. 62, no. 7, pp. 1785-1793, July
2015. doi: 10.1109/TCSI.2015.2441966.
[81] S. Bae, Y. Kim, Y. Park, and C. Kim, " 3-Gb/s high-speed true random
number generator using common-mode operating comparator and
sampling uncertainty of D flip-flop, " IEEE J. Solid-State Circuits, vol. 52,
no. 2, pp. 605-610, Feb. 2017. doi: 10.1109/JSSC.2016.2625341.
[82] J. Kim et al., " Nano-intrinsic true random number generation: A
device to data study, " IEEE Trans. Circuits Syst. I, Regular Papers, vol. 66,
no. 7, pp. 2615-2626, July 2019. doi: 10.1109/TCSI.2019.2895045.
[83] F. Rahman, B. Shakya, X. Xu, D. Forte, and M. Tehranipoor, " Security
beyond CMOS: Fundamentals, applications, and roadmap, " IEEE
Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 12, pp. 3420-3433,
Dec. 2017. doi: 10.1109/TVLSI.2017.2742943.
[84] R. Govindaraj, S. Ghosh, and S. Katkoori, " CSRO-based reconfigurable
true random number generator using RRAM, " IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 26, no. 12, pp. 2661-2670, Dec. 2018.
doi: 10.1109/TVLSI.2018.2823274.
[85] B. Lin et al., " A high-speed and high-reliability TRNG based on
analog RRAM for IoT security application, " in Proc. IEEE Int. Electron
Devices Meeting, San Francisco, 2019, pp. 14-18.
[86] Z. Wei et al., " True random number generator using current difference
based on a fractional stochastic model in 40-nm embedded ReRAM, " in
Proc. IEEE Int. Electron Devices Meeting, San Francisco, Dec. 2016, pp. 4-8.
[87] Y. Wang, H. Cai, L. A. Naviner, J. O. Klein, J. Yang, and W. Zhao, " A
novel circuit design of true random number generator using magnetic
tunnel junction, " in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures,
Beijing, 2016, pp. 123-128.
[88] M. Barangi, J. S. Chang, and P. Mazumder, " Straintronics-based
true random number generator for high-speed and energy-limited applications, "
IEEE Trans. Magn., vol. 52, no. 1, pp. 1-9, Sept. 2015. doi:
10.1109/TMAG.2015.2478398.
THIRD QUARTER 2021
[89] B. Ray and A. Milenkovic, " True random number generation using
read noise of flash memory cells, " IEEE Trans. Electron Devices, vol. 65,
no. 3, pp. 963-969, Mar. 2018. doi: 10.1109/TED.2018.2792436.
[90] S. Larimian, M. R. Mahmoodi, and D. B. Strukov, " Lightweight integrated
design of PUF and TRNG security primitives based on eFlash
memory in 55-nm CMOS " , IEEE Trans. Electron Devices, vol. 67, no. 4,
pp. 1586-1592, Apr. 2020. doi: 10.1109/TED.2020.2976632.
[91] Z. Liang, H. Wei, and T. Liu, " A wide-range variation-resilient physically
unclonable function in 28 nm, " IEEE J. Solid-State Circuits, " vol. 55,
no. 3, pp. 817-825, Mar. 2020. doi: 10.1109/JSSC.2019.2942374.
[92] S. Satpathy et al., " A 4-fJ/b Delay-hardened physically unclonable
function circuit with selective bit destabilization in 14-nm Trigate
CMOS, " IEEE J. Solid-State Circuits, vol. 52, no. 4, pp. 940-949, Apr. 2017.
doi: 10.1109/JSSC.2016.2636859.
[93] H. N. Noura, R. Melki, and A. Chehab, " Secure and lightweight mutual
multi-factor authentication for IoT communication systems, " in
Proc. IEEE Int. Conf. Veh. Technol., Honolulu, HI, 2019, pp. 1-7.
[94] S. Banerjee, V. Odelu, A. K. Das, S. Chattopadhyay, J. J. P. C. Rodrigues,
and Y. Park, " Physically secure lightweight anonymous user
authentication protocol for internet of things using physically unclonable
functions, " IEEE Access, vol. 7, pp. 85,627-85,644, 2019.
[95] M. H. Mahalat, S. Saha, A. Mondal, and B. Sen, " A PUF based light
weight protocol for secure WiFi authentication of IoT devices, " in Proc. IEEE
Int. Symp. Embedded Comput. Syst. Design, Cochin, India, 2018, pp. 183-187.
[96] Y. Gao, D. C. Ranasinghe, S. F. Al-Sarawi, O. Kavehei, and D. Abbott,
" Emerging physical unclonable functions with nanotechnology, " IEEE
Access, vol. 4, pp. 61-80, 2016. doi: 10.1109/ACCESS.2015.2503432.
[97] S. Sutar, A. Raha, and V. Raghunathan, " Memory-based combination
PUFs for device authentication, " Forensics Security, vol. 14, no. 4,
pp. 1109-1123, Apr. 2019.
[98] Y. Tanaka, S. Bian, M. Hiromoto, and T. Sato, " Coin flipping PUF: A
novel PUF with improved resistance against machine learning attacks, "
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 5, pp. 602-606, May
2018. doi: 10.1109/TCSII.2018.2821267.
[99] S. S. Zalivaka, A. A. Ivaniuk, and C. Chang, " Reliable and modeling
attack resistant authentication of arbiter PUF in FPGA implementation
with trinary quadruple response, " IEEE Trans. Inf.
[100] M. Cortez, S. Hamdioui, A. Kaichouhi, V. Leest, R. Maes, and G.
Schrijen, " Intelligent voltage ramp-up time adaptation for temperature
noise reduction on memory-based PUF systems, " IEEE Trans. Comput.Aided
Design Integr. Circuits Syst., vol. 34, no. 7, pp. 1162-1175, July 2015.
doi: 10.1109/TCAD.2015.2422844.
[101] L. Kusters and F. M. J. Willems, " Secret-key capacity regions
for multiple enrollments with an SRAM-PUF, " IEEE Trans. Inf. Forensics
Security, vol. 14, no. 9, pp. 2276-2287, Sept. 2019. doi: 10.1109/
TIFS.2019.2895552.
[102] A. Schaller et al., " Decay-based DRAM PUFs in commodity devices, "
IEEE Trans. Dependable Secure Comput., vol. 16, no. 3, pp. 462-475,
May 2019. doi: 10.1109/TDSC.2018.2822298.
[103] B. Talukder, B. Ray, D. Forte, and M. T. Rahman, " PreLatPUF: Exploiting
DRAM latency variations for generating robust device signatures, "
IEEE Access, vol. 7, pp. 81,106-81,120, 2019.
[104] N. Kumar, J. Chen, M. Kar, S. K. Sitaraman, S. Mukhopadhyay, and
S. Kumar, " Multigated carbon nanotube field effect transistors-based
physically unclonable functions as security keys, " IEEE J. Internet Things,
vol. 6, no. 1, pp. 325-334, Feb. 2019. doi: 10.1109/JIOT.2018.2838580.
[105] M. Kim, D. Moon, S. Yoo, S. Lee, and Y. Choi, " Investigation of physically
unclonable functions using flash memory for integrated circuit
authentication, " IEEE Trans. Nanotechnol., vol. 14, no. 2, pp. 384-389,
Mar. 2015. doi: 10.1109/TNANO.2015.2397956.
[106] L. Zhang, X. Fong, C. Chang, Z. H. Kong, and K. Roy, " Optimizating
emerging nonvolatile memories for dual-mode applications: Data storage
and key generator, " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,
vol. 34, no. 7, pp. 1176-1187, July 2015. doi: 10.1109/TCAD.2015.2427251.
[107] C. Labrado and H. Thapliyal, " Design of a piezoelectric-based
physically unclonable function for IoT security, " IEEE J. Internet Things,
vol. 6, no. 2, pp. 2770-2777, Apr. 2019. doi: 10.1109/JIOT.2018.2874626.
[108] R. Liu, H. Wu, Y. Pang, H. Qian, and S. Yu, " A highly reliable and
tamper-resistant RRAM PUF: Design and experimental validation, " in
Proc. IEEE Int. Symp. Hardware-Oriented Security Trust, McLean, VA,
2016, pp. 13-18.
[109] S. Ben Dodo, R. Bishnoi, S. Mohanachandran Nair, and M. B.
Tahoori, " A spintronics memory PUF for resilience against cloning
IEEE CIRCUITS AND SYSTEMS MAGAZINE
29
IEEE Circuits and Systems Magazine - Q3 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2021
