IEEE Circuits and Systems Magazine - Q3 2021 - 33

voltage that will not disturb the memory states and
overhead of the digital-to-analog converter (DAC), the
input precision is typically implemented by multiple
cycles in practice. For example, an 8-bit input could
be represented by 8 cycles with additional shift-andadd
process. Therefore, there may be two rounds of
shift-and-add peripheral circuits (one for weight significance
and one for input significance). The output
precision before the first round shift-and-add is determined
by the ADC resolution.
To represent both positive and negative weights,
there are a couple of methods: 1) using a complementary
pattern of two memory cells (e.g. in two adjacent
columns) or two differential sub-arrays. Subtraction
between the two columns or two sub-arrays either in
analog manner before the ADC or in digital manner after
the ADC is performed; 2) using a dummy column where
the memory cells are programmed to the median level
of conductance range of the multilevel cell (or using on/
off states of two binary cells that are combined for average).
Then the maximum positive/negative weights (i.e.
+1/-1) are mapped to the maximum/minimum conductance
of the memory cell. Similarly, subtraction between
the data column and the dummy column either in analog
manner before the ADC or in digital manner after the
ADC is performed; 3) Using two's complement code if
the memory cell is binary. The first bit is thus becoming
the sign bit. CIM array performs unsigned VMM first and
then utilizes the periphery to obtain correct output according
to the scale and sign information.
VMM essentially performs read operation to the memory
sub-array. To program the weights to initialize DNN
model for subsequent inference or to update the weights
during in-situ training, write operation is conducted in
the memory sub-array (typically in a row-by-row fashion).
Fully parallel write scheme is possible [9], [10], but
huge power consumption to write the entire sub-array
simultaneously may be prohibitive in practice. Write-verify
is commonly used to accurately tune the conductance
of the memory cells for inference [11] [12].
1.2. Comparison with Digital MAC
or Near-Memory Compute
It is worthwhile to compare CIM with other related approaches
for deep learning acceleration such as digital
MAC and near-memory compute as shown in Fig. 2.
Digital MAC approach refers to designs that follow
similar principles as TPU. Notable pioneering examples
include MIT's Eyeriss [13], KU Leuven's Envision [14] and
KAIST's UNPU [15]. A digital MAC based accelerator typically
consists of many PEs based on digital multipliers
and adders. All the weights and input/output activations
are temporarily stored in global buffer (i.e. SRAM cache)
and local registers, while they are fetched to the PEs for
actual MAC operations. Dataflow is optimized to reuse
the weights/inputs/outputs and minimize their movements
in the digital MAC architecture. Near-memory
compute is similar as CIM which also has a weight stationary
dataflow, but the weights are read-out in a rowby-row
fashion and weighted sum is computed at a local
Layer i
Layer i+1
IN[0]
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Figure 1. Schematic of compute-in-memory (CIM) paradigm. A layer of neural network is mapped to the memory sub-arrays.
Inputs are loaded in parallel as voltage to activate multiple rows, and column currents are summed up and digitalized by analogto-digital
converter (ADC).
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
33
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IEEE Circuits and Systems Magazine - Q3 2021

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