IEEE Circuits and Systems Magazine - Q3 2021 - 34

accumulator placed at edge of the sub-arrays [16]. Hence,
near-memory compute is essentially a purely digital design,
as opposed to the mixed-signal nature of CIM. A
recent benchmark study systematically compared the
three approaches at the same technology node, showing
that CIM with eNVM outperforms digital MAC and nearmemory
compute with SRAM in throughput and energy
efficiency [17]. There are also near-memory compute or
CIM designs that employ standalone memories such as
dynamic random access memory (DRAM) [18], [19] or
3D NAND Flash memory [20], sometimes such approach
is referred to as processing-in-memory (PIM) [21]. Due
to the fabrication incompatibilities with advanced logic
process, these designs could only employ limited resources
of peripheral circuitry on the commodity DRAM
or NAND Flash dies, thus they are best suited as a coprocessor
to compute VMM workloads offloaded from
the host processor. Heterogeneous integration such as
through-silicon-via (TSV) or hybrid bonding between
co-processor and host-processor may be required to
realize the full system functionality. We will not discuss
such PIM designs in this article and our focus is on the
single-die solution where the embedded memories are
integrated with extensive logic processing units on the
same chip for in-memory computing.
1.3. Embedded Memory Technology Choices
To implement CIM, mature SRAM technology (possibly
with modified bit cell) has been leveraged. SRAM is primarily
used as the on-chip cache in microprocessors
and has enjoyed the benefits of scaling together with
logic transistors to today's 5 nm node [22]. Large on-chip
SRAM capacity (i.e., 256 Mb = 32 MB demonstrated occupying
only 5.38 mm2 for memory cells) is demonstrated at
5 nm [22]. Therefore, advantage of using SRAM for CIM is
the commercial foundry availability at the latest technology
node (soon in 3 nm or beyond). Proposals using embedded
DRAM (eDRAM) for near-memory compute have
been made [23]. Unfortunately eDRAM is not widely available
in industry platforms (only offered in Intel's 22 nm
[24] and IBM/Globalfoundries' 14 nm [25]). There are
also custom designs using 4T as eDRAM [26] or 3T-1C as
eDRAM [27] for CIM. However, SRAM/DRAM is inherently
volatile, and consumes significant standby leakage power
or refresh power, especially when the dynamic power
gating is desired in edge devices. In this context, eNVM
technologies may become more competitive on powerconstrained
platforms, as they could be turned on and off
instantly without losing the stored weights. In addition,
an eNVM cell typically has a smaller layout area than an
SRAM cell and possibly offers multi-bit per cell, yielding a
higher integration density at the same technology node.
eNVMs of interests here include resistive random access
34
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
Pool, Activation
INPUT
ProcessElement
(PE)
REG
CTRL
Fort MAC,
Control, etc
SA
PE PE
(a)
Ctrl
Adder + Register
PE
(b)
Figure 2. Schematic of (a) digital MAC accelerator and (b) near-memory compute and CIM accelerators.
PE
Ctrl
Global Buffer
PE PE
W
W
Parallel MAC
IO (ADC)
PE
Row-by-Row Read
Near Memory Computing
Pool, Activation
Local Buffer
PE
Input
CIM
DRAM
WL Driver
DRAM
WL Driver
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