IEEE Circuits and Systems Magazine - Q3 2021 - 36

SRAM is considered as a viable candidate from the technology availability's
perspective. To be compatible for CIM, innovation of the bit-cell is required.
Titan RTX GPU [53] has ~61.4 TOPS/W; TPU v1 [2] for
cloud has ~76.8 TOPS/W; edge TPU [54] has ~128 TOPS/W;
TPU for training [55] has ~115 TOPS/W.
2.1. SRAM Based CIM Bacros
SRAM is considered as a viable candidate from the
technology availability's perspective. To be compatible
for CIM, innovation of the bit-cell is required. With
aggressive scaling, it is possible to hold most of the
weights on-chip (e.g. 128 Mb SRAM demonstrated at
10 nm [56], 256 Mb SRAM demonstrated at 7 nm [57],
256 Mb SRAM demonstrated at 5 nm [22]). Enlarging
on-chip SRAM capacity is helpful to minimize off-chip
DRAM access. To enable CIM, SRAM is typically modified
from the conventional 6-transistor (6T) bit cell.
The variants of commonly used SRAM bit cells for CIM
are shown in Fig. 3.
For activation based on ReLU, only 0 or positive input
are used. Therefore, a conventional 6T cell is feasible
as shown in Fig. 3(a). First both BL and BLB will be precharged.
If the input is " 1 " , WL is asserted, then BL and
BLB will be discharged with different amounts of current:
a small discharge current if Q is " 1 " and a large discharge
current if QB is " 0 " . When multiple rows are turned on,
BL and BLB will decay from VDD with different rates, and
their voltage when SA is enabled represents the analog
MAC result. If the input is " 0 " , WL remains off thus no
current contribution to both BL and BLB. Multi-bit input
could be represented as WL voltage, but its analog
values need to be fine-tuned to guarantee linear spacing
between current levels through the pass gate transistors.
One reliability issue of the 6T cell is read-disturb
when multiple WLs are activated simultaneously. If BL
or BLB voltage is pulled down to a low level too quickly
due to large discharge current, SRAM cells storing " 1 "
may suffer from flipping. Another issue for the 6T cell is
asymmetric data pattern for partial sum accumulation.
The product of input " 1 " (applied to the pass-gate) and
weight " 0 " (stored in the cell) has different impact on
discharge current than the product of input " 0 " (applied
to the pass-gate) and weight " 1 " (stored in the cell). The
analog output representing " 0 " varies according to different
input and weight data patterns. To eliminate the
reference mismatch for ADC quantization, input-aware
dynamic reference generation is employed [58].
For XNOR-Net [59] where both input and weight are
binarized to +1/-1, negative inputs are required. Therefore,
one simple modification to 6T cell is to split WL
and WLB, where WL is applied to Q and WLB is applied
to QB, as shown in Fig. 3(b). As the inputs to WL and
WLB are always complementary, only one of the pass
gate transistors will be turned on. Therefore, only one
of BL and BLB will have discharge current. This will
help save the energy consumption, and also help enlarge
the sense margin compared to the conventional
6T cell where both BL and BLB decay. The cell layout
overhead of 6T split cell is minimal with additional
WLB interconnect routing.
To solve read-disturb issue, 8T read-decoupled bit cell
is preferred but at noticeable expense of additional layout
area, as shown in Fig. 3(c). Write operation is performed
on the conventional 6T cell. Two more pass-gate transistors
are added in series to BL for read operation. Only
when RWL and Q are both " 1 " , the pull down path is enabled
to discharge RBL. This structure makes a large voltage
swing on BL to increase the sense margin without disturbing
internal storage node to the 6T core. In addition,
the 8T cell does not need dynamic reference scheme.
To enable bi-directional access in on-chip training,
8T transposable bit cell is proposed, by adding two
Conventional 6T
Split 6T
WLB
QB Q
WL
BLB
(a)
BL
BLB
(b)
QB Q
WL
BL
WBLB
WBL
(c)
Figure 3. Schematic of variants of SRAM bit cells that are proposed for CIM.
36
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
8T Read Decoupled
QB Q
RBL
BLB
RWL
BLT
BL
QB Q
BLBT
WL
(d)
WLT
``
Transposable 8T
IEEE Circuits and Systems Magazine - Q3 2021

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