IEEE Circuits and Systems Magazine - Q3 2021 - 37

sets of pass-gate transistors with orthogonal WLT and
BLT/BLBT on top of a conventional 6T cell, as shown
in Fig. 3(d). For backpropagation, the input are applied
to vertical WLT, additional two pass-gate transistors are
enabled for read-out from horizontal BLT/BLT.
Table 1 surveys the recent SRAM based CIM macros
that were taped-out into silicon. General trends include
aggressive scaling from 130 nm to 7 nm, supporting
MAC operations from binary to 8-bit, improving the
normalized energy efficiency from ~50 TOPS/W to
~5000 TOPS/W, and achieving simple MNIST dataset
with merely ~91% accuracy to CIFAR-10 dataset with
reasonable ~91% accuracy. It should be pointed out a
few observations: 1) the sub-array size is often limited
to 64 if the rows are fully turned on. Some macros reported
up to 512 sub-array size if the rows were partially
turned on [60] or just using row-by-row read-out [61];
2) throughput of the macro depends on the total memory
capacity, and some designs [62] with large on-chip
SRAM capacity could support parallel operations on
many sub-arrays thereby achieving higher throughput;
3) most of the demonstrations used software/hardware
mixed experiments, which computed MAC on the macro
while utilizing FPGA or testing equipment for control of
the rest digital processing (e.g. batch norm, activation,
pooling, etc.). Therefore, the reported energy efficiency
Table 1.
Survey of recent SRAM based CIM macros that were taped-out into silicon.
VLSI' 16
Princeton [63]
130
ISSCC' 18
NTHU [58]
Technology (nm)
Cell structure
Bit-cellsize(F2)
Subarray size
Capacity
Precision(I,W,O)
Supported
algorithm
Energy efficiency
Throughput
Accuracy
inference or
training
Technology (nm)
Celli structure
Bit-cellsize(F2)
Subarray size
Capacity
Precision(I,W,O)
Supported
algorithm
Energy efficiency
Throughput
Accuracy
Inference or
training
65
C6T
254
128 × 128
16 Kb
5,1,1
Linear classify
57.85 TOPS/W
182.2 GOPS
91%(MNIST)
Inference
ISSCC' 18
MIT [66]
65
10T
N/A
256 × 64
16 Kb
7,1,7
CNN
196.7 TOPS/W
74.9 GOPS
98%(MNIST)
Inference
S6T
125
64 × 64
4 Kb
1,1,3
XNORNN/BNN
65
6T
N/A
512 × 256
128 Kb
8,8, N/A
SVM
111.6 TOPS/W 200 TOPS/W
1.78 TOPS
264 GOPS
97.5%(MNIST) N/A
Inference
DAC' 18
ASU [64]
65
8T
183
64 × 64
4 Kb
1,1,3
XNOR-BNN
50 TOPS/W
1.78 TOPS
87.46%
(ClFAR10)
Inference
Training(digital)
ISSCC' 19
NTHU [67]
55
Twin-8T
548
64 × 60
3.75 Kb
4,5,7
CNN
ISSCC' 18 UIUC
[61]
VLSI' 18
ASU/Columbia [65]
65
12T
923
256 × 64
16 Kb
1,1,3
XNOR-NN
403 TOPS/W
N/A
85.7% (ClFAR10)
Inference
ISSCC' 20
NTHU ]60]
28
6T+Transposablecell
210
512 × 128
64 Kb
8,8,20
CNN
734.8 TOPS/W 972 TOPS/W
424 GOPS
269 GOPS
90.42%
(ClFAR10)
Inference
Note: Energy efficiency & Throughput is normaiized to Ibit MAC (lb MAC = 2 operations)
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
37
91.94% (ClFAR10)
Training
VLSI' 18
Princeton [62]
65
8T+Cap
N/A
N/A
2.4 Mb
1,1,1
BNN
658 TOPS/W
9.43 TOPS
83.27%
(ClFAR10)
Inference
ISSCC' 20
TSMC [68]
7
8T
1081
64 × 64
4 Kb
4,4,4
CNN
5136 TOPS/W
5.9 TOPS
98.6%(MNIST)
Inference
IEEE Circuits and Systems Magazine - Q3 2021

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