IEEE Circuits and Systems Magazine - Q3 2021 - 38

In summary, SRAM is a mature candidate for CIM, with
state-of-the-art process availability at 5 nm or beyond.
is only measured on the macro itself (instead of on the
entire system). Key features of these representative designs
are summarized as follows.
As a pioneering work of SRAM based CIM, standard
6T SRAM array was modified to perform MAC operation
in parallel [63]. A split-6T cell design was proposed
[58] where the two pass-gate transistors are controlled
by two different WLs and only one WL and its associated
BL are turned on during the parallel read-out
operation, so that energy consumption can be reduced
by around 50% as compared to the conventional 6T
bit cell. A variant of design on this chip is 8T-XNOR
bit cell [64] where additional two pass-gate transistors
crossly-coupled BL and BLB to efficiently implement
XNOR-Net [59], one of the representative binary neural
networks. Another design that implements XNOR-Net
used a custom 12T bit cell [65]. Rather than currentdomain
compute, metal-oxide-metal capacitors above
SRAM bit cells were also proposed for charge-domain
accumulation [62]. Conv-RAM [66] proposed 10T bit
cell design to overcome read disturb and used inherent
BL capacitance to store multiplication results. With
novel DAC and time-domain ADC design, it supported
multi-bit MAC operations. Twin-8T design [67] supported
multi-bit in-cell analog shift and add. In this
design, two read-decoupled 8T cells are used to form
a twin-cell (M8T, L8T). The transistor width of multiplication
branch in M8T is twice of that in L8T to provide
twice weighted cell current, thus each Twin-8T (T8T)
cell could represent 2-bit. To support 5-bit weight, two
T8T cells (MT8T and LT8T) with one sign cell (S8T) are
grouped using two's complement coding. To represent
multi-bit input, it uses different RWL voltage levels. 3
levels are used to tune the pass-gate current linearly,
corresponding to 2-bit input. If two cycles are used
with shift-add peripheral circuitry, 4-bit input could be
supported. To summarize, this Twin-8T design enables
5-bit signed weight and 4-bit unsigned input. A recent
design implemented efficient training by designing a
transposable SRAM array architecture, which could
support bidirectional MAC operations [60]. Each processing
unit includes 1 transpose-multiply-cell (TMC)
and 16 regular 6T SRAM cells. Each TMC consists of 10
transistors including 2 pass-gate transistors and 2 multiply
branches. TMC has two read modes to support bidirectional
bitwise multiplication so that forward and
backward propagation calculation can be implemented
in the same array. TSMC recently implemented a CIM
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IEEE CIRCUITS AND SYSTEMS MAGAZINE
macro with 8T read decoupled bit cell in 7 nm FinFET
technology [68]. Each row has a 4-bit digital counter
which converts the 4-bit input value into number of
RWL pulses. 4 bit weight is realized by charge sharing
among binary-weighted computation capacitors. Each
unit of computation capacitors is formed by the inherent
capacitor of sense amplifier. Every 4 RBLs share
one 4-bit Flash ADC. Compensation capacitors are
added on each RBL so that each RBL contains equal
lumped capacitance.
In summary, SRAM is a mature candidate for CIM,
with state-of-the-art process availability at 5 nm or beyond.
Impressive energy efficiency has been shown in
the aforementioned silicon prototype chips. However,
leakage power will be the main concern for large-capacity
SRAM arrays. 6T SRAM is the most compact bit cell,
but read disturb is present when multiple rows are activated.
Lowering WL voltage will help, but the number of
rows that can be turned on is limited (e.g. up to 64). 8T
SRAM decouples read-write paths thus offers more flexibility
for CIM design. Foundry typically offers 6T and 8T
SRAM compact design rule. If further changing the bit
cell (e.g. adding more transistors or changing the interconnect
routing), the logic design rule that is handcrafted
has to be employed, resulting in much lower density
(2×~4×) from layout's perspective. In old technology
node (e.g. 65 nm), there are more room to modify the bit
cell and reroute interconnect, but in advanced technology
node (e.g. 28 nm or beyond), foundry typically does
not offer exceptions for making these changes. Therefore,
splitting the rows into multiple sub-groups and
then embed the compute-cell between groups seems a
viable approach to enable more sophisticated functions
(e.g. transposable read) as demonstrated in [60]. Moving
one step further from a single CIM macro prototype
to the full system demonstration, a functional DNN processor
that integrated multiple 8T read decouple SRAM
arrays with additional digital processing blocks and buffers
has been reported [69].
2.2. RRAM Based CIM Macros
RRAM is a two-terminal variable resistor based on metal/oxide/metal
structure whose resistance can be tuned
by the programing voltage pulses between high-resistance
state (HRS) and low resistance state (LRS) [70]
[71]. RRAM process is silicon CMOS compatible, and it
is typically integrated at the back-end-of-line (BEOL)
fabrication as a contact via between two metal layers.
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