IEEE Circuits and Systems Magazine - Q3 2021 - 4

Feature
Hardware Security Exploiting
Post-CMOS Devices:
Fundamental Device
Characteristics, State-ofthe-Art
Countermeasures,
Challenges and Roadmap
Aditya Japa1, Student Member IEEE,
Manoj Kumar Majumder1, Senior Member IEEE,
Subhendu K. Sahoo2, Member IEEE,
Ramesh Vaddi3, Senior Member IEEE,
Brajesh Kumar Kaushik4, Senior Member IEEE
Abstract
Emerging nanoelectronic semiconductor devices have been quite
promising in enhancing hardware-oriented security and trust.
However, implementing hardware security primitives and methodologies
requires large area overhead and power consumption.
Furthermore, emerging new attack models and vulnerabilities are
regularly evolving and cannot be adequately addressed by current
CMOS technology. This paper for the first time presents a comprehensive
review of numerous post-CMOS technologies based
hardware security primitives and methodologies, particularly true
random number generators, physically unclonable functions, sidechannel
analysis countermeasures, and hardware obfuscation
techniques. Various beyond-CMOS device technologies including
tunneling FET (TFET), hybrid phase transition FET (HyperFET),
carbon nanotube FET (CNTFET), silicon nanowire FET (SiNWFET),
symmetrical tunneling FET (SymFET), phase-change
memory (PCM), spin-transfer torque magnetic tunnel junction
(STT-MTJ), resistive random access memory (RRAM) have been
considered in this study. First, the basic principle of operation
and unusual characteristics of nanoelectronic devices used for
hardware security applications have been extensively discussed.
Later, CMOS technology challenges and benefits of emerging
Digital Object Identifier 10.1109/MCAS.2021.3092532
Date of current version: 12 August 2021
4
IEEE CIRCUITS AND SYSTEMS MAGAZINE
1531-636X/21©2021IEEE
THIRD QUARTER 2021

IEEE Circuits and Systems Magazine - Q3 2021

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