IEEE Circuits and Systems Magazine - Q3 2021 - 40

the ADC size. Smaller multiplexing ratio results in better
throughput at sub-array level, but still it is generally
less competitive than SRAM counterparts partly due to
column sharing and partly due to slower inherent sensing
speed in RRAM; 4) ADC resolution has a wide range
from 1 bit to 8 bit; 5) Similarly as SRAM, most of the demonstrations
here used software/hardware mixed experiments.
Therefore, the reported energy efficiency is only
measured on the macro itself. Key features of these representative
designs are summarized as follows.
As a pioneering work of RRAM-based CIM macro [79],
a two-macro (nvCIM-P and nvCIM-N) structure was proposed
to support binary-input and ternary-weighted network.
The nvCIM-P macro stores positive weights while
the nvCIM-N stores negative weights. Weight " 0 " is encoded
as HRS, while weight " +1 " is encoded as LRS in nvCIM-P,
and " -1 " as LRS in nvCIM-N. Digital inputs are applied
via WL. MAC values along BLs which refer to the number
of product " ±1 " are differentiated using a multi-level
current sense amplifier. A binary-input/ binary-output
Table 2.
Survey of recent RRAM based CIM macros that were taped-out into silicon.
ISSCC' 18
NTHU [79]
65
1
VLSI' 18
PSCS [80]
Technology (nm)
No. of bit per cell
Subarray size
Capacity
Precision(I,W,O)
Column sensing
# of rows turned on
Supported
algorithm
Energy efficiency
Throughput per
readout
Accuracy
Inference or
training
Technology (nm)
No. of bit per cell
Subarray size
Capacity
Precision(I,W,O)
Column sensing
# of rows turned on
Supported
algorithm
Energy efficiency
Throughput per
readout
Accuracy
Inference or
training
40
ISO
8
512 × 256
1Mb
1,1,3
3b ADC
9
CNN
38.4TOPS/W
1.82 GOPS
98% (MNIST)
Inference
SSCL' 20 ASU/
GT[83]
90
2
128 × 64
8Kb
1,2,1
1b SA
64
CNN
N/A
4Mb
1,8,1
1b SA
N/A
MLP
N/A
ISSCC' 19
NTHU [78]
55
1
256 × 512
1Mb
2,3,4
4b ADC
9
CNN
165,6 TOPS/W 131.4 TOPS/W
4.98 GOPS
90.8% (MNIST)
Inference
ISSCC' 20
Tsinghua [84]
130
2
N/A
158.8Kb
1,3,8
8b ADC
N/A
MLP
N/A
8S.5%(CIFAR10)
Inference
ISSCC' 20
Stanford [86]
130
Analog
256 × 256
64Kb
1, analog, 1
I & F spiking
N/A
ANNs; PGMs
102.8 TOPS/W 235.2 TOPS/W 148 TOPS/W
35.6 GOPS
N/A
87.1%(CIFAR10)
Inference
94.4% (MNIST) N/A
Inference
Inference
Note: Energy efficiency & Throughput is normaiized to Ibit MAC (lb MAC = 2 operations)
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
ISSCC' 20
NTHU [85]
22
1
512 × 512
2Mb
4,4,11
6b ADC
16
CNN
242,76 TOPS/W
14 GOPS
90.18% (CIARIO)
Inference
VLSI' 20
Stanford [82]
130
1
256 × 256
N/A
2,1, N/A
N/A
16-96
CNN
N/A
N/A
91,38% (MNIST)
Inference
TED' 20
ASU/GT [81]
90
1
128 × 64
8Kb
1,1,3
3b ADC
64
CNN
24,1 TOPS/W
19.7 GOPS
83.5% (CIFARIO)
Inference
Nature' 20
Tsinghua [46]
130
3
128 × 128
1Mb
8,4,8
8b ADC
128
CNN
352 TOPS/W
N/A
94,08%
(CIFAR10)
Training(FCN)

IEEE Circuits and Systems Magazine - Q3 2021

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