IEEE Circuits and Systems Magazine - Q3 2021 - 41

RRAM-based CIM design was presented in [80]. This
work stores weights as analog resistance and binarizes
output with a simple sense amplifier. However, only simple
multilayer perceptron (MLP) has been demonstrated,
achieving low-inference accuracy for MNIST. CIM design
is desired to support multiple-bit precision for more complex
networks. As a solution, a serial-bit input parallelbit
weight structure was proposed in [78] to optimize the
area-speed-power tradeoff. N-bit inputs are sequentially
fed into the single cell array in N cycles. Multi-bit weight
is stored in multiple cells at the same row. To generate
the BL current with appropriate significance, a currentmirror
based structure is employed to collect the weighted
sum of all the currents along the read-path. A downscaling
current translator was implemented to reduce the
amount of current to achieve short delays, small offset
and compact area. Instead of employing two macros to
store negative and positive weight separately, XNORRRAM
[81] employed 2T2R (two vertically adjacent 1T1R)
bit cell to represent positive/negative weights, eliminating
analog or digital subtractor in the periphery. A voltage
divider is formed between a PMOS pull up header and
pull down networks through RRAM cells. Voltage-mode
Flash ADC was employed to solve limited-parallelism
caused by large BL current. In this work, 64 WLs could be
turned on simultaneously thereby improving throughput
substantially. A similar design with 2T2R bit cell encoded
one weight as differential conductance states on adjacent
rows rather than adjacent columns [82]. By making SL
floating internally, charge redistribution will occur and
the resulting SL voltage will represent the MAC result.
This modification improves energy efficiency by avoiding
static current from VDD to ground. To further improve
integration density and energy efficiency, designs of 2-bit
per cell RRAM array were also demonstrated [83] [84].
More aggressively, 3-bit per cell was exploited in [46] to
support in-situ training of a fully connected neural network
to circumvent device non-idealities. To efficiently
support high-precision requirement, a BL-IN-OUT multibit
computing scheme was proposed in [85]. Previous
approaches suffered from limited parallelism due to wide
range of BL current and long latency in multiple cycles of
binary serial-inputs. In this work, a 4-bit input is split into
two sequential 2-bit signals as the inputs of BL clamping
to shorten access time. Besides, instead of positivenegative-split
weight mapping, the proposed scheme use
the 2's complement coding which requires only 4 1T1R
cells to store each signed 4-bit weight. BL current is determined
by the product of input-aware BL voltage and
RRAM cell conductance. The MAC operation of 2-bit input
and 4-bit weight can be finished in one cycle. A recent
design [86] demonstrated that RRAM-based CIM array
could implement not only convolutional neural networks
THIRD QUARTER 2021
(CNNs) but also probabilistic graphical models (PGMs)
and recurrent neural networks (RNNs).
In summary, 1T1R or 2T2R is the typical bit cell for
RRAM based CIM. The cell area typically ranges from
30F2 to 60F2, which is about 3× to 6× higher density than
SRAM at the same technology node for CIM. In principle,
RRAM cell area could be 6F2 or 10F2 if using DRAM or NOR
Flash design rule. However, the high voltage and large
write current make the access transistor larger than
the minimum size. RRAM has a potential for multilevel
cell (MLC) operation, though the MLC reliability needs
further optimization (e.g. relaxation after programming,
drift of the resistance, retention at high temperature,
etc.). RRAM still faces challenges of high programming
voltage (especially in the forming process) and low LRS
resistance. Typically iterative write-verify is needed for
accurate programming the resistance states, making it
viable for inference only but difficult for in-situ training.
RRAM scaling lags behind SRAM, state-of-the-art RRAM
is available at 22 nm node (from TSMC and Intel), which
may be a sweet spot for low-cost edge platforms.
3. General Design Challenges for CIM
3.1. Analog-to-Digital Conversion Bottleneck
As shown in most reported CIM designs, ADC is a major
bottleneck for area/power efficiency. Fig. 5 shows the
layout of RRAM based CIM macro [83] and its power
breakdown, indicating that ADC occupies significant
portion. The resolution of ADC is determined by the
partial sum precision required from sub-array, which
Level Shifters
Mux
RRAM
Array
Control Circuits
(Decoder, etc.)
Power
18.7%
VDD = 1.2 V
RRAM Arrays With ADCs
Control Circuits, Mux,
Level Shifters
81.3%
Figure 5. Layout of the RRAM CIM macro in [83] showing the
peripheral circuit area overhead and its power breakdown.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
41
ADC
IEEE Circuits and Systems Magazine - Q3 2021

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