IEEE Circuits and Systems Magazine - Q3 2021 - 42

is then affected by the number of rows that are turned
on simultaneously and the memory cell precision. When
a large weight matrix is partitioned into several subarrays,
partial sums are obtained from multiple sub-arrays
and then accumulated. By quantizing partial sums
in the VGG-8 model, Fig. 6 shows the inference accuracy
of CIFAR-10 dataset as a function of the ADC resolution
for different sub-array sizes and memory cell precisions.
Since partial sum distribution is empirically centered in
the middle, either nonlinear quantization [64] or linear
quantization with reduced dynamic range [87] is helpful
to lower the required ADC resolution. Typically the
DNN model could tolerate certain degree of resolution
reduction of partial sums. It should be pointed
out that ADC for CIM does not require super-high resolution,
3-6 bit is generally sufficient for CIFAR-10 dataset.
On the other hand, there is a stringent requirement
on the area of ADC, as ideally each column needs to be
equipped with one ADC to maximize the parallelism
of VMM. It is very difficult to achieve the column pitch
matching from layout point of view due to a relatively
large size of ADC and a small column pitch of sub-array
(especially for RRAM). Therefore, column time multiplexing
is required. In the reported macros, 8:1 MUX [81]
or even 32:1 MUX [78] is used for RRAM array, which
significantly reduces the throughput.
Considering these requirements, Flash-ADC and successive-approximation
ADC (SAR-ADC) are widely used
for CIM. In principle, ADCs could be built with voltagemode
or current-mode comparators or sense amplifiers
with different references [88]. Here we employ a
simple voltage-mode comparator to explore trade-offs
between Flash-ADC and SAR-ADC. Fig. 7 shows the
SPICE simulation results of SAR-ADC and Flash-ADC in
terms of area, latency, power, and energy for different
resolutions. The simulations are performed using TSMC
40 nm PDK with the following assumptions: sub-array
size is 128 × 128, RRAM cell's on-state resistance (Ron)
is 100 kΩ, and on/off ratio is 100. To make a fair comparison,
a thermometer-to-binary encoder is included
in the Flash-ADC design while the output of SAR-ADC
is naturally binary code. As shown in Fig. 7, the area of
SAR-ADC only slightly increases when the resolution
goes up due to additional overhead from the SAR-logic
module. As expected, the area of Flash-ADC increases
exponentially due to an exponential growth of the number
of comparators deployed. Nevertheless, Flash-ADC
holds the advantage of short latency, i.e., potentially
higher throughput, compared to SAR-ADC. The latency
of Flash-ADC remains the same while SAR-ADC's latency
increases linearly with the resolution. Another drawback
for Flash-ADC is large power consumption which
exponentially increases with resolution while SAR-ADC
has power dissipation nearly irrespective to resolution.
Considering energy-efficiency of the conversion
per sampling, Fig. 7 also compares energy consumption
between two designs where the energy number is
averaged from various input samples (i.e., the number
of Ron cells along the column varies from 1 to 128). It
can be observed that the average energy consumption
of Flash-ADC is slightly larger than that of SAR-ADC
when resolution is 3-bit and the difference dramatically
increases with higher resolutions. Generally, taking
the balance between energy consumption and latency
into consideration, i.e., the energy-delay product metric
(EDP), Flash-ADC has better performance for lower resolution
(3-bit or below) while SAR-ADC performs better
for higher resolution (4-bit or above).
90
90
Baseline: 92%
60
60
Array Size
64 × 64
30
30
3-Bit
4-Bit
ADC Precision
(a)
1-Bit/Cell
5-Bit
3-Bit
4-Bit
ADC Precision
(b)
2-Bit/Cell
4-Bit/Cell
Figure 6. ADC resolution requirements for inference at sub-array size of (a) 64 × 64; (b) 128 × 128 and (c) 256 × 256. Simulation
for VGG-8 model on CIFAR-10 dataset.
42
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
5-Bit
3-Bit
4-Bit
ADC Precision
(c)
5-Bit
Array Size
128 × 128
30
Baseline: 92%
60
Array Size
256 × 256
90
Baseline: 92%
Inference Accuracy (%)
Inference Accuracy (%)
Inference Accuracy (%)

IEEE Circuits and Systems Magazine - Q3 2021

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