IEEE Circuits and Systems Magazine - Q3 2021 - 43

Recent advances have been made to perform as much
analog compute as possible before converting to the
digital processing thereby mitigating ADC overhead. For
example, one effective technique is to perform the analog
shift-and-add before the ADC for different significant bits
in the weight precision [68]. This could potentially save
Vin
Flash ADC
DAC
2N - 1 Comparators
Thermometer
to
Binary Encoder
CLK
VDAC
Vin
S/H
-
+
Dn-1 Dn-2
D1 D0
SAR Logic
Digital
Output
SAR ADC
1,400
1,200
1,000
800
600
400
200
34
1
2
3
4
5
6
7
8
56
Resolution (Bit)
(a)
Power (mW)
10
12
14
16
2
4
6
8
34
56
Resolution (Bit)
(c)
SAR
FLASH
Figure 7. Comparison between SAR-ADC and Flash-ADC on (a) area, (b) latency, (c) power, and (d) energy. Simulated performed
at 40 nm.
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
43
34
56
Resolution (Bit)
(d)
Energy (pJ)
Area (µm2)
14
12
10
8
6
4
2
34
56
Resolution (Bit)
(b)
Latency (ns)
Reference Inputs
COMP
COMP
COMP
N-Bit
Digital Output
COMP

IEEE Circuits and Systems Magazine - Q3 2021

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