IEEE Circuits and Systems Magazine - Q3 2021 - 48

48
IEEE CIRCUITS AND SYSTEMS MAGAZINE
THIRD QUARTER 2021
Python Wrapper
(b)
(a)
DNN Setup
# of Pulse
3
2
1
(c)
Forward
Retention Model
G Drift
Log (t)
%
90
85
80
ADCADC ADC
Inference
Accuracy
104 105 109
(d)
Chip Floorplan
Global
Peripherals
Unroll
(f)
Assign Traces to HW w/
Array-Partitioning
Layer-1
Tiles
G Map
-1 01
Figure 10. Framework structure of DNN+NeuroSim. (a) DNN setup in python wrapper; (b) during training, introducing non-ideal properties of synaptic devices, including nonlinearity,
asymmetry, device-to-device, and cycle-to-cycle variation in the weight update; (c) during inference, introducing retention model and ADC quantization effects; (d) pre-defined network
structure is loaded as input to NeuroSim core, for automatic floor-planning with weight-duplication to maximize memory utilization; (e) loading real trace (synaptic weights and neural
activations) into NeuroSim, mapping data to conductance and digital voltage input cycles; (f) to be partitioned and assigned to different locations of the CIM system; (g) hierarchical
simulation from chip to tile, and from processing element (PE) to synaptic array.
Matrix
Layer-N
Transfer
Traces
Synaptic
Array
(e) Activation
Sec
ADC Quantization
Effect
Kernels
NeuroSim Core
Synaptic
Array
-128
%
90
80
20
Inference
Accuracy
ADC Prec
23 4
ADC Ref
Partial
Sum
128
Python Wrapper
* Setup DNN Structure
* Train DNN Model
* Nonlinearity
* C2C, D2C Variation
* Run Inference
* Save Real Traces
* Neural Activation
* Synaptic Weight
 Inference Accuracy
 Training Accuracy
(g)
NeuraSim Core
* Chip Floorplan
* Map Weight to HW
* Array Size, Ron/Roff
* ADC Precision
* Write Voltage/Pulse
* # Write Pulse LTP/LTD
* Hardware Estimation
 Area, Latency,
Energy, Leakage
 Energy Efficiency
Throughput
Hierarchical Simulation
Chip
Tile
PE
2 Pulses
# of Pulse
Pulse #
ADCADC ADC
-6
LTD
Weight Update
Variation
Pulse #
Synaptic
Array
3
3 Pulses
2
1
Define
# Pulse
Linearly
Non-Ideal
Weight Update
Model:
LTP
6
Nonlinearity
Asymmetry
Variations
Deviceto-Device
Weight
Update
Variation
Pulse #
Cycleto-Cycle
Max
Memory Utilization
Network Structure
Synaptic Weight and
Neural Activations
Log (G)
Gmin Gmax
Back-Propagation
Conductance
Count
Conductance
Normalized
Conductance
Normalized
Conductance
Normalized
Conductance

IEEE Circuits and Systems Magazine - Q3 2021

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