IEEE Circuits and Systems Magazine - Q3 2021 - 49

FeFET [110]) as shown in Table 4.
SRAM/TPU-like based CIM accelerators
are evaluated at both 22 nm and
7 nm, and eNVM based CIM accelerators
are evaluated at 22 nm, as 22 nm
is state-of-the-art node where the
eNVMs are integrated. Level shifters
to provide high write voltage are
included for eNVM based designs.
4-bit per cell
is assumed for PCM
and FeFET except the 2-bit RRAM
from the previously discussed CIM
macro [83]. The benchmark results
show that, large on-state resistance
Ron
is the key factor to achieve better
energy efficiency. To avoid large
voltage drop, transistors in 1T1R or
peripheral mux have to be sized up
for small Ron, yielding significant area
overhead. As a result, it takes longer
time to activate sub-arrays (due to
the increased BL capacitance loading),
adversely increasing latency
and lowering throughput. Therefore,
conventional filamentary switching
RRAM with a couple kΩ [83] is not
competitive. On the other hand, if
Ron is too high, the latency will be too
long due to excessive RC delay. Therefore,
synaptic devices with Ron range
(100 kΩ~1 MΩ) (e.g. interface-engineered
RRAM [109] or FeFET [110])
are highly desired. It should be noted
that at 22 nm eNVM-CIM designs
generally could achieve >3× superior
energy efficiency (in TOPS/W) than
22 nm SRAM-CIM design. However,
7 nm SRAM-CIM design achieves the
least chip area (thus the best compute
efficiency in TOPS/mm2). For highperformance
applications (e.g. in the
data-center enviro nment), the latest
SRAM technology is still a top choice.
Now the question becomes when
22 nm eNVM-CIM designs could be
significantly more attractive over
7 nm SRAM-CIM design. The above
benchmark assumes continuous inference
without any pause in the operations.
But in smart edge devices,
if we consider the frequent standby
mode, then advantages of eNVMs
will show up as SRAM is always
THIRD QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
49
Table 4.
Benchmark results of CIM accelerators on VGG-8 for CIFAR-10, based on SRAM (at 7nm and 22nm) and reported eNVM devices (assumed at 22 nm).
VGG-8 (8-bit activation; 8-bit weight) on CIFAR10
Technology node (LP)
Device
Flash-ADC precision
Memory Cell Precision
Ron (Ω)
On/Off Ratio
Inference Accuracy (%)
Area (mm2)
Memory Utilization (%)
L-by-L Latency (ms)
L-by-L DynamicEnergy (uJ)
L-by-L Leakage power (mW)
Energy Efficiency (TOPS/W)
Compute Efficiency (TOPS/mm2)
0.63
22.86
1.47
51.100
0.144
13.61
8T-SRAM
4-bit
1-bit
7 nm
TPU-like
(Google)
MAC
\
\
92%
15.71
39.36%
0.53
245.81
75.96
2.510
0.075
59.05
98.73%
0.76
56.56
1.11
21.360
0.027
60.78
96.86%
0.79
33.14
0.17
36.980
0.026
33.26
93.47%
0.61
17.24
0.09
71.170
0.061
8T-SRAM
8-bit vdigital 4-bit
1-bit
RRAM
(Winbond)
5-bit
2-bit
6k
150
RRAM
(Tsinghua)
5-bit
4-bit
100k
10
22 nm
PCM (IBM)
5-bit
4-bit
40k
12.5
91%
33.39
93.47%
0.61
17.85
0.09
68.730
0.060
32.69
93.47%
0.61
16.28
0.09
75.360
0.060
Si:HfO2
FeFET (GF)
5-bit
4-bit
240k
100
TPU-like
(Google)
8-bit digital
MAC
\
\
92%
107.05
39.36%
0.75
381.27
5.27
1.610
0.008
IEEE Circuits and Systems Magazine - Q3 2021

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