IEEE Circuits and Systems Magazine - Q3 2021 - 62

■ the set of the engineering data which are physical
parameters of materials;
■ the use of ANSYS Mechanical to build a solid state
model, which allows temperature field calculations
as the solutions to stationary and non-stationary
thermal contact and heat radiation effects;
■ the generation of the finite element mesh by ANSYS
Meshing.
The Solving stage includes 3 steps:
■ the choose of the analysis type, which is SteadyState
Analysis, and options;
■ the define of boundary condition types (thermal
and electrical);
■ the define of calculation parameters.
The last stage deals with the output of calculated and
simulated results in tables and graphs.
The 3D model of a thermoelectric generator core
chip is shown in Fig. 9. The model elements are listed in
the figure caption. The core of a thin-film TEG consists
of two plates with n-type and p-type semiconductor
thermoelements arranged on it. The silicon substrates
are used as plates. The geometrical dimensions of thermoelements
are determined in accordance with the required
output power. The assessment showed that with
an output power of 25 μW, the dimensions of a thermoelement
with 288 units will be 20 × 60 × 60 microns. The
TEG core chip is placed on a printed circuit board and
sealed between two aluminum parts of the package. The
top part of the cylindrical package functions as a radiator.
The bottom part is made in the form of a rectangular
plate to which a printed circuit board with the chip is
attached along with the contact pads. A dielectric ring
separates the bottom and top parts of the package. The
size of the TEG core chip is 3.8 × 2.7 × 0.8 mm and the size
of the assembled generator is 15 × 10 × 0.7 mm.
In accordance with the simulation results, the prototype
chip of the TEG has been fabricated. The fabrication
process consists of the following stages [20]: a TEG main
part (lower) fabrication, a TEG commutation part (upper)
fabrication, a flip-chip bonding and a packaging. The fabrication
process scheme of a core chip is shown in Fig.10.
Stage 1. A TEG chip base is made of a silicon wafer with
an oxide film. Contact areas are formed by magnetron sputtering
onto an oxide film to form an electrical connection
between semiconductor thermoelements. Each contact
area consists of three layers: Cr-Cu-Ti. Chromium thin
film serves as an adhesion layer between silicon dioxide
and copper. A titanium layer functions as a seed layer
4
Si/SiO2
1
Cr Cu Ti
2
(a)
Sb2Te3
3
Bi2Te3
(b)
0,000 0,500 1,000 (mm)
0,250 0,750
(a)
32
1
4
0,000
0,500 1,000 (mm)
0,250 0,750
(b)
Figure 9. 3D model of a thermoelectric generator core chip
(a) front view, (b) side view: 1 - silicon substrate, 2 - n- and
p-type thermoelements, 3 - contact area, 4 - load resistance.
62
IEEE CIRCUITS AND SYSTEMS MAGAZINE
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(c)
Figure 10. Illustration of the fabrication process flow of a thinfilm
TEG core chip: the bottom substrate with Cr-Cu-Ti metallization
(a), An electrodeposition of the n-type and the p-type
thermoelements (b), Flip-chip bonding (c).
THIRD QUARTER 2021
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IEEE Circuits and Systems Magazine - Q3 2021

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