IEEE Circuits and Systems Magazine - Q3 2021 - 8

the current increases abruptly with an increase in VGS
due to the low resistance of PTM. This transition from
insulator to metal results in the hysteresis in IVD
GS characteristics
of HyperFET that can be observed in Fig. 3(b).
These hysteresis and abrupt transition characteristics of
Hypertext have been explored to enhance the security of
crypto engines against DPA [56].
B. TFET Unique Characteristics
Tunnel FET (TFET) has emerged as a promising device
candidate for future electronic circuit design
that achieve ultra-low energy consumption [43]. It's
structure is identical to gated p-i-n tunnel diode with
asymmetrical source/drain doping as shown in
Fig. 5(a). TFET operates exploring band-to-band tunneling
mechanism while reverse biasing gated p-i-n
structure. In the recent experimental demonstration,
TFET exhibited a high
II /ON OFF ratio and steep subthreshold
swing (<60mV/dec) at lower supply voltages
[49]. Among several proposed TFETs, III-V TFETs
attracted wide attention because of higher ON current
[57]. In this work, a look-up table based 20nm
InAs TFET Verilog-A model
is
Introduction
Section I
Overview and Motivation of Post-CMOS
Based Hardware Security
Post-CMOS Devices and Characteristics
Section II
HyperFET
Transistors
TFET
SiNWFET
CNTFET
SymFET
Unique Characteristics
Hysteresis, Ambipolarity, p-i-n Forward
Current, Inherent Variations, Low-Leakage
Process Variations, Resistance
Variability, Programming
Sensitivity, Stochastic Nature
Challenges of CMOS Based Hardware Security Countermeasures
State of the Art
Section III
Physically Unclonable
Functions
Side-Channel Analysis
Countermeasures
True Random Number
Generators
Hardware Obfuscation
Technique
Benefits of Post-CMOS Devices Based Hardware Security
Countermeasures
Discussion on Post-CMOS Based Hardware Security
Section V
Section IV
Challenges And Roadmap
Summary of Post-CMOS Devices
Based Hardware Security
Countermeasures
Section VI
Conclusion
Figure 3. Structure and organization of paper.
8
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Memory Devices
PCM
STT-MTJ
RRAM
explored to generate the peculiar
characteristics that are leveraged
for hardware security applications
[57].
The ambipolarity is an inherent
property of TFET and it is due
to the reverse tunneling at the
drain channel junction [49]. The
magnitude of ambipolar current
mainly depends on the drain-side
doping concentration and drain
extension length. With the heavily
doped drain region, one can
achieve the onset of tunneling for
both positive and negative gate
bias. Figure 5(b) presents the
IVD
GS characteristics of InAs NTFET
showing significant tunneling
current for
VGS =- and 0.5V.
05V
.
By proper biasing of source, drain,
and gate, a TFET can function either
as n-type or p-type device.
Similarly, Silicon nanowire FET
(SiNWFET) with ultra-thin body
structure and lightly doped channel
provides the ability to change
the carrier type in the channel
by utilizing gate [58]. Further, it
has been revealed that the TFET
exhibits significant p-i-n forward
leakage with an increase in negative
drain-to-source voltage bias
[59]. Figure 5(c) illustrates the
IVD
DS characteristics of NTFET
showing significant p-i-n forward
current transport instead of the
unidirectional current conduction
with negative
V .DS With a positive
V ,DS TFET exhibited identical characteristics
to that of CMOS device.
At large negative
V ,DS due to
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