IEEE Circuits and Systems Magazine - Q1 2022 - 26

4) Finite Impulse Response (FIR) Feedback DACs
Regardless the ADC quantization is realized in either
amplitude or time domain, it presents a number of inconveniences
in terms of analog circuit complexity and the
nonlinearity caused by mismatches in the feedback DAC.
To address this problem, some authors propose the use
of alternative implementations of the modulator feedback
DAC waveforms-such as a DAC with a Finite Impulsive
Response (FIR) [91], [93], [205], [206]. The idea -originally
proposed in [207] and conceptually illustrated in
Fig. 14-is to feedback a filtered version of the single-bit
quantization output, such that due to the high-frequency
attenuation of the FIR filter, the DAC output is a multi-level
waveform. This way, using a single-bit ADC and a FIR
DAC allows to obtain the low-jitter sensitivity and high
linearity of a multi-bit RDM, while keeping the simplicity
and robustness of single-bit RDMs as well as a reduced
analog circuit content [206], [208]. Moreover, the combination
of Time-Interleaved (TI) topologies [209] and FIR
DACs is a promising approach to implement RDM-based
GHz-range and RF-to-digital converters [210]. Thus, FIR
DACs reduce the analog content of the ADC and make it
easier to digitally control its specifications by using an
ANN algorithm as pretended in AI-managed digitizers.
5) Fully Depleted Silicon-on-Insulator (FDSOI)
Technologies
The aforementioned digital-assisted analog techniques
can benefit from the use of nanoscale technologies such
as FDSOI. This process is postulated as one of the key
technologies for mobile telecom applications, thanks to
its better performance than bulk CMOS in terms of transit
frequency (),fT
transconductance efficiency (),d
gm/I
reduced
impact of passive parasitic elements, as well as improved
noise isolation. Another great potential of FDSOI is
its enhanced body effect by a wider tuning of the threshold
voltage,
V ,th which makes it possible to reduce the voltage
ranges to supply voltages in the order of a few hundreds of
mV [211], thus increasing the performance metrics of ASP
in communications, including the enhanced linearity of
frequency/time-based circuits [212].
VI. Circuit Examples: Programmable RDMs for
AI-Managed CR Digitizers
As an application of the circuits and systems techniques
discussed above, let us consider two RDM examples
and case studies which can be applied to implement
mostly-digital, highly programmable digitizers for
SDR/CR transceivers. Two circuit examples are shown
to illustrate their application in the CR-based receivers
shown in Fig. 13, i.e. a DCR receiver with a programmable
LP-RDM ADC and a widely tunable BP-RDM for RFto-digital
conversion. In the latter case, an example of
26
IEEE CIRCUITS AND SYSTEMS MAGAZINE
how LSTM-based AI engines can be used to manage the
electromagnetic spectrum and reconfigure their operation
in CR-based receivers will be shown.
A. Reconfigurable SC-RDM for DCR-Based
SDR/CR Systems
Let us consider first the use of RDMs for the design of
reconfigurable baseband ADCs in DCR-based receivers.
Fig. 13(a) shows the block diagram of such a receiver
for SDR/CR, where after being filtered and preamplified,
incoming RF signals are downconverted to baseband,
where they are digitized by a reconfigurable LP-RDM
ADC. In this example, the receiver aims to cover the requirements
of diverse wireless standards including in
4G such as GSM, Bluetooth, GPS, UMTS, DVB-H, WLAN,
LTE, among others. These standards involve digitizing
signals with Bw
ranging from hundreds of kHz to hundreds
of MHz with an ENOB within 12 to 8 bit, respectively.
A Switched-Capacitor (SC) RDM will be considered
to highlight its high programability feature-one of
the main characteristics required to implement AI-managed
CR devices. The required programmable requirements
can be addressed by properly reconfiguring a SC
RDM with a loop-filter order of
=
quantization of B = 1-to-3 bit, and an OverSampling Ratio,
OSR
! (, )
10 200 [64], [213]-[215].
1) Modulator Architecture
The conceptual RDM considered in this example-
shown in Fig. 15-consists of a N-stage MASH topology,
where all stages can be made independently switchable
according to the desired quantization noise shaping, and
the Digital Cancellation Logic (DCL) can be programmed
according to the value of L [214]. If a stage is turned off,
its building blocks can be powered down to save power.
The number of bits of the internal quantizers, i.e.,
B ,i
and/or the OSR can be also reconfigured to increase the
flexibility of the ADC. In addition to its reconfigurable
characteristics (OSR, L and B), a multimode RD ADC
should be able to digitize signals corresponding to different
standards-for instance, GSM and Bluetooth signals
and WLAN signal-in a simultaneuous or concurrent
way. Indeed, concurrency can be also implemented in
a MASH RDM, as shown in Fig. 15, where a switchable
SC network is used to allow the ADC to be configured
as several sub-ADCs, working in parallel-each one processing
a different input signal [214].
2) Programmability at Circuit Level
Several alternative RDM topologies can be considered
for the ADC in Fig. 15, by properly combining 2nd-order
stages and 1st-order stages in order to guarantee
the stability of each sub-modulator [213], [216]. Fig. 15
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L ,, ,24 6 an embedded
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