IEEE Circuits and Systems Magazine - Q1 2022 - 59
is determined based on the analog
voltage, and the measured two-way
ranging is shown in Fig. 27. The integrated
TRX can enable UWB communications
and localization at the
same time with a compact size. A
UWB transceiver SoC is presented
in Fig. 18(d), which can simultaneously
enable accurate localization
at <15 cm resolution and energyefficient
communications for WSN,
WPAN, and WBAN with 0.92 nJ/b for
TX and 5.3 nJ/b for RX at 1Mb/s data
rate [38]. The integrated radio platform
can operate under OOK, BPSK,
and ternary coding modes aiming at
various kinds of applications.
F. Integrated Wideband FSK/
GMSK/QPSK/π/4-DQPSK TX
Integrated wideband transmitters
which can operate in different modes
are necessary for highly efficient
communications. Moreover, DLLs
need to be specifically designed
to ensure precise synchronization
[139]-[142]. In [139], a TX operating
in 400 MHz implemented with
phase-interpolated dual-injection
(PIDI) DLL-based synthesizer is proposed
to enable applications covering
varying data rates in accordance to
the IEEE 802.15.6 Wireless BodyArea-Network
(WBAN) standard.
The TX can support FSK/MSK/
GMSK and BPSK/QPSK/π/4-DQPSK
modulations compliant with the
IEEE802.15.6 WBAN standard [139].
The TX can support a data rate up to
20 Mb/s according to proprietary protocols
[139]. The die photograph of
the transceiver is shown in Fig. 18(e).
The system can achieve an imTransmitted
Data
Pattern
100 Mb/s
Emitted
Data Pattern
Recovered
Data Pattern
Transmitted
Data Pattern
200 Mb/s
Emitted
Data Pattern
Recovered
Data Pattern
Figure 23. Measured TRX outputs (data rate 100Mb/s and 200Mb/s) [35] © 2006 IEEE.
RX
LNA
LPF
RX
LO_I
LPF
RX
LO_Q
Antenna
Frequency
Generator
To
RX
Buffer
DA
TX
TX LO
Figure 24. 802.1.5.4a transceiver system architecture [37] © 2008 IEEE.
proved SNR by multi-channel sampling.
A 100-ps resolution can be enabled by the triple
delay-locked loop (DLL) [32]. The schematic of the multimode
multi-channel TX is shown in Fig. 28, where the
essential building block is the PIDI synthesizer, which
is realized by the hybrid finite impulse response (FIR)
architecture [139]. The tunability on frequency can be
enabled to support multi-channel operation. A 15b delta-sigma
modulator with a two-bit output is leveraged
to randomly select DLL phase edges from 0{ to 11{ for
FIRST QUARTER 2022
Tuning
Fine
Coarse
Tuning
Multi-Tone VCO
Buffer
Modulator BPSK
To
TX
Burst
Control
TX Clk
TX Data
VGA
Squ.
Squ.
2
+ LA
LPF
ADC
ADC
Ranging
RC Clk
RX Data
VGA
2
ADC
Baseband
RX Data
Bb+
Bb-
Dig+
Dig-
Mod+ Mod-
Figure 25. BPSK modulator [37] © 2008 IEEE.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
59
TX/RX Switch
Biquad
Buffer
First
Order
IEEE Circuits and Systems Magazine - Q1 2022
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