IEEE Circuits and Systems Magazine - Q2 2022 - 14

TwA xt St Ay tS txy
+()
()
St =-R dxx ttx
=- () ()
and () ()St =-R dyy tty
(12)
where x(t) and y(t) are the pre- and postsynaptic traces.
() ()
are the preand
postsynaptic spike trains. Thus, from Equation 12
and Figure 8(a), the weight is increased at the moment
of postsynaptic firing by an amount that depends on the
value of the trace x(t) left by the presynaptic spike. Similarly,
the weight is depressed at the moment of presynaptic
spikes by an amount proportional to the trace y(t) left
by previous postsynaptic spikes. This has been shown to
fit the experimental data as shown in Figure 8(b) and [95],
and has been studied in [12], [102], [103].
The most straightforward way to implement supervised
learning is to use Hebbian Learning [77], [104].
Supervision is introduced in Hebbian learning by an additional
'teaching' signal that reinforces the postsynaptic
neuron to fire at the target times and to remain silent at
other times. The 'teaching' signal is usually transmitted
to the neuron in a form of synaptic currents or as intracellularly
injected currents.
Another approach is to utilize a supervised learning
algorithm for ANNs called backpropagation. BackpropaPre
Post
Pre
Post
Pre
Post
Pre
Post
(a)
0.0075
0.005
0.0025
-0.0025
-0.005
-0.0075
-0.01
-40
-20
∆t (ms)
(b)
Figure 8. (a) STDP and (b) its profile.
14
IEEE CIRCUITS AND SYSTEMS MAGAZINE
20 40
gation, a gradient-based optimization algorithm, is a standard
training technique for ANNs. However, it cannot be
directly applied to the in-hardware learning of an SNN running
on a neuromorphic processor due to several reasons;
(1) spiking neuron's activities are not differentiable, (2) the
connections between neurons in SNNs are unidirectional
such that a backward path must be added explicitly with
constantly updated weights during learning, (3) errors in
ANNs are propagated as real values and (4) weight update
of a synapse is not solely dependent on locally available
information as required in a neuromorphic hardware
[105]. There have been various approaches to adopt the
backpropagation algorithm to train deep SNNs directly
[13], [33], [36], [106]-[108]. One category of approaches
keeps track of the membrane potential at spike times
and back-propagate errors based on that. SpikeProp
[109] is the first attempt to train an SNN using such an
approach. But SpikeProp is limited to single-spike learning.
A similar category of approaches [13], [110] treats
the discontinuities during spike times as noise and
smoothens the membrane potential to essentially make
it continuous. These approaches utilize spike-rate to
compute the loss and membrane potential to compute
the error derivative, and hence create a discrepancy.
[106] proposed an event-driven random backpropagation
(eRBP) algorithm simplifying the backpropagation
chain path. But this work requires multicompartmental
neurons to enable error to locally modulate plasticity.
In [107], a supervised learning method was proposed
(BP-STDP) where the backpropagation update rules were
converted to temporally local STDP rules for multilayer
SNNs. Recently, Error-Modulated STDP (EMSTDP) [108],
[111] was proposed to approximate backpropagation
in the spike domain for neuromorphic implementation.
This work applies the same type of integrate and fire (IF)
neuron in the forward and backward path, and enhances
the biological plausibility of backpropagation algorithm
by introducing a weight update rule that resembles the
rate-based STDP using only the locally available information.
Its learning capability has been demonstrated on
the Loihi processor [111].
III. Neuromorphic System Design Considerations
To design a neuromorphic processor, a complete ecosystem
including both software and hardware needs to
be considered. This does not only include the hardware
implementation of neurons and synapses, and their communication
network, but also simulators and compilers
for design validation and optimization.
A. Neuron and Synapse Implementations
A bottom-up approach is generally adopted in neuromorphic
hardware design. Neurons and synapses are the
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