IEEE Circuits and Systems Magazine - Q2 2022 - 18

neuron and synapse models that they support, their implementation
choices, architecture and software support
is provided in Table II.
A. Digital ASIC: TrueNorth
TrueNorth is a brain-inspired digital chip with an interconnected
network of 64x64 neurosynaptic cores, where
each core has 256 incoming axons, a 256x256 synapse
crossbar, and 256 neurons [138] as shown in Figure 10(a).
In total, there are 1 million spiking neurons and 256
million synapses in a TrueNorth chip. Binary synapses,
with programmable weights, gate the information flow
from axons to neurons. Each axon fans out to all neurons
in a core in parallel, thus, providing a 256-fold reduction in
communication volume in comparison to a point-to-point
approach. TrueNorth implements these intra-core connections
through SRAM crossbar memory whereas intercore
connections are implemented through spike-based
message-passing network. Programmability of TrueNorth
in terms of neuron parameters, synaptic crossbar connections,
and inter-core connectivity allows a wide range of
structures, dynamics, and behaviors.
1) Neuron and Synapse Implementation
TrueNorth's neuron model is based on the classic leaky
integrate-and-fire neuron (LIF) with five basic operations:
synaptic integration, leak integration, threshold comparison,
spike generation, and membrane potential reset. The
Table II.
Design Choices in the Large-Scale Neuromorphic Systems.
Neuron
TrueNorth
Loihi
Classic LIF
CUBA LIF
Synapse
Binary with a choice
of four 8-bit weights
Variable precision
weight, allows PSP
with exponential
kernel filter
SpiNNaker
Any
Any
Implementation
Choice
Digital
Digital
Architecture
256x256 crossbar per
core, 64x64 core array
No crossbar, 1048
neurons per core, 128
cores
Digital,
Multiprocessor
SOC
BrainScaleS
Exponential
IF (AdExp)
-
Analog/Mixed
signal
-
Software Support
Matlab-based
object-oriented
Corelet language
Python-based
API NxSDK, also
supported by
Nengo
SpiNNaker API,
PyNN, Nengo,
NEST, Brian,
sPyNNaker
A wafer with 56x8 ANC
containing ANNCORE,
each of which has
128k synapse and 512
membrane circuits
Tianjic
Classic LIF -
Digital
2D mesh many-core
with 156 Fcores, each
with 32 weight index and
256 fan-ins/fan-outs
18
IEEE CIRCUITS AND SYSTEMS MAGAZINE
PyNN
membrane potential () of the neuron j is updated acVtj
cording
to these five operations as summarized in Equations
13, 14 and 15.
Synaptic integration:
N
Vt Vt
Leak integration:
Vt Vt
If Vt $ a
jj jm=- () ()
Membrane potential reset:
() ,()
jj spikeand jj
Vt R
=
(14)
(15)
For each of the neurons, membrane potential is the accumulated
sum of the product of spike input to the synapse
()
Sti
at the current timestep and the signed synaptic
weight x .i Following integration, the LIF neuron model
subtracts the leak value jm from the membrane potential
every timestep. This linear leak operation serves as a
constant bias on the neural dynamics. The neuron fires a
spike and resets its membrane potential to Rj
(typically,
Rj is zero), when the membrane potential of the LIF neuron
at the current timestep () is greater than or equal
to the neuron threshold voltage aj .
Vtj
This LIF neuron model is augmented by configurable
and reproducible stochasticity [117]. Each individual
neuron can be configured to have stochastic synaptic input,
leak, and threshold to enable rich dynamics across
jj 1=- +
() () ()/ St x
i
=
-
1
ii
(13)
-
SECOND QUARTER 2022
IEEE Circuits and Systems Magazine - Q2 2022

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