IEEE Circuits and Systems Magazine - Q2 2022 - 20

mesh to serialize exiting spikes and deserialize entering
spikes. This enables scaling the two-dimensional
mesh across chip boundaries as tiles, similar to the
mammalian neocortex.
The architecture is efficient because neurons that
form a cluster can be mapped to the same neuron core
and communicate using local connections. The remaining
inter-core connection is sparse, which reduces the communication
cost. Additionally, each spike event addresses
a pool of neurons on a target core, reducing the number of
long-range spike events. The tile based architecture also
increases the fault tolerance, as the system usability is
not disrupted by occasional defects at the core and chip
level. Also, the architecture is flexible as each neuron is
individually configurable, each synapse can be turned on
or off individually, and the neurons and synapses support
programmed stochastic behavior. Thus, the neuron model
[117] supports a wide variety of computational functions
and biologically relevant spiking behaviors. One of
the limitations of the architecture is that, to reduce the
hardware cost, each column in the crossbar supports
only 4 different synaptic weights, ranked from 1-4; and
all synaptic connections in the same row must select the
weight in the same rank in the corresponding column.
3) Supporting Software/Software Ecosystem
A TrueNorth program is a complete specification on the
connectivity and configurations of a network of neurosynaptic
cores, along with its external inputs and outputs.
The " corelet " , abstraction is used to represent a
TrueNorth program by only exposing external inputs and
outputs while encapsulating all other details of the network
of neurosynaptic cores as shown in Fig. 10(b). The
object-oriented Corelet Language is developed by IBM
for creating, composing, and decomposing corelets. As
part of the TrueNorth ecosystem, a Corelet Library that
provides a repository of reusable corelets macros, and
an end-to-end Corelet Laboratory that is a programming
environment integrated with the TrueNorth architectural
simulator are also provided [258]. In 2016, IBM released
the Eedn deep learning framework [36] to facilitate the
training and mapping of deep spiking neural network on
the TrueNorth system.
Eedn-trained CNNs have matched state-of-the-art accuracy
on benchmarks that previously required floatingpoint
precision and unconstrained connectivity, while
achieving throughput of 1,200-2,600 classifications on CIFAR
dataset per second and power consumption of only
25-275 mW [36] on 2000 to 4000 cores. TrueNorth systems
have been applied to real time handwritten character recognition
and confabulation [70], anomaly detection [260],
optical flow [261], unconstrained optimization [262], decoding
EEG [263], medical image segmentation [264], etc.
20
IEEE CIRCUITS AND SYSTEMS MAGAZINE
B. ASIC with on-Chip Learning: Loihi
Loihi [105] is a digital neuromorphic chip recently developed
by Intel. Loihi is fabricated in Intel's 14-nm process.
A Loihi chip contains 128-neuromorphic cores totaling
130,000 artificial current-based (CUBA) leaky-integrateand-fire
neurons and 130 million synapses. It also provides
a programmable microcode learning engine for
on-chip SNN training. A Loihi chip consists of 3 Lakemont
cores, which help with implementing advanced learning
rules and managing the neuromorphic cores. The Loihi
design supports scaling up to 4,096 on-chip cores and
16,384 chips.
1) Neuron and Synapse Implementation
Loihi adopts a variation of the CUBA LIF model that has
two internal state variables, the synaptic response current
()
uti
vti
tic response current is given by the sum of filtered input
spike trains and a constant bias current:
uw ()()
ji
it
() / ij uj
,
()
=- x
-
u
u Ht
=+a )
=Y
St bi
(16)
where wij is the synaptic weight from neuron j to i,
ax 1
response parameterized by the time constant ux with H(t)
the unit step function, ()
Stj
indicates the convolution operation, and bi
bias. As shown in Eq. 16, the same kernel ()tua
all synapses of the postsynaptic neuron u. The synaptic
current is further integrated into the membrane potential
based on Eq. 17, and the neuron spikes when its membrane
potential passes its firing threshold
ii .
vt 1
Sti
i +=-+ - iii ii
xv
()
() ()
1 vt ut St
()
(17)
where () is the output spike of the neuron. As shown
in Eq. 17, the integration is leaky, as captured by the time
constant
xv . vi is initialized with a value less than ii , and
is reset by ii after a spiking event occurs.
Each synapse in Loihi is configured by a 5-tuple:
(, ,, ,)
ij weight delaytag , where i, j are the source and destination
neuron indices of the synapse, and weight, delay
and tag are integer-valued properties of the synapse. Synaptic
delays enable advanced temporal codes by delaying
the accumulation of an incoming spike, while tags are useful
as an additional scratch variable within the learning
engine. Each synapse also associates with multiple presynaptic
traces, and whereas compartment with postsynaptic
traces. They use different exponential smoothing
parameters with decay a and impulse magnitude d and
are evaluated as follows:
xt ad St
xt
66 6@@ @$$1=- +
(18)
SECOND QUARTER 2022
uttpex (/ )( ) is the synaptic filter impulse
is the input spike train, " * "
is a constant
is used by
and the membrane potential (). The synap
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