IEEE Circuits and Systems Magazine - Q2 2022 - 22

capacitors/inductors, basic operations of neural computation
such as conservation of charge, amplification,
exponentiation, integration, thresholding, etc., can be
naturally emulated [4]. Such analog/mixed-signal design
has the potential to achieve higher speedup and energy
efficiency than digital systems. Some representative
analog/mixed-signal neuromorphic computing systems
are: BrainScaleS, BrainDrop, NeuroGrid, DYNAP-SEL etc.
Though these systems differ in various aspects, they
share the same design philosophy. They all use analog
circuits to implement neuron and synapse models for efficient
computation and implement control, on-chip communication,
I/O, data storage using digital circuits. They
also adopt multi-core architecture and NoC for parallelism
and scalability. In this section, we take BrainScaleS as
an example to introduce neuromorphic computing hardware
using analog/mixed-signal design.
BrainScaleS is a part of Human Brain Project's (HBP)
neuromorphic computing platform. HBP is a brain research
initiative supported by the European Union, aimed
at facilitating research of human brain related areas, such
as neuroscience, medical research, cognitive science
as well as brain-inspired computing technologies [276],
[277]. HBP neuromorphic computing platform offers two
complementary systems: BrainScaleS and SpiNNaker.
BrainScaleS implements neuron and synapse models using
analog circuits, enabling low power and high speed at
the cost of flexibility. SpiNNaker, which will be discussed
in Section IV-D, on the other hand, is based on general purpose
ARM processors, providing flexible functionalities.
1) SNN Models
BrainScales implements an exponential integrate and fire
model (AdExp) [278], [279] as below:
-= -dt
C
-mldV
gV Eg d exp
ll
-=xwldw wa VE
dt
! +
Where C ,m
g ,l E ,l
Ee
+- +- +
cm
gt VE gt VE wt
()
()
()() ()()
ee ii
th
VVth
dth
-
ww b upon generating aspike
and Ei
(20)
(21)
(22)
are the membrane capacity,
leakage conductance, leakage, excitatory and inhibitory
reversal potentials respectively [280]. ()
gte
2
and () repgti
resent
the total excitatory and inhibitory synaptic conductance.
Vth is the threshold, when
VV ,th the AdExp
neuron potential can develop to infinity rapidly, d th determines
sharpness of the procedure. Equation 21 depicts the
evolution of adaption current. w is increased by b, which
is called spike triggered adaption, upon generating a spike.
x w
is a time constant and a is subthreshold adaptation efficacy.
By ignoring the exponential term and the adaption,
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IEEE CIRCUITS AND SYSTEMS MAGAZINE
the AdExp models can be simplified to the common leaky
integrate and fire model. More details about how the neuron
model is implemented can be found in [279].
2) Hardware Platform
The full BrainScaleS-1 system (NM-PM-1) consists of
20 neuromorphic wafer modules and peripheral devices
such as support infrastructure for power, communication
and analog readout. An additional computer cluster is
used to control the wafer modules [281].
The underlying building block of the BrainScaleS system
is the High Input Count Analog Neural Network chip
(HICANN), which is an uncut 20 cm wafer scale chip fabricated
by 180 nm CMOS technology [280]. HICANN adopts
mixed signal design. Computations of neurons and synapses
are carried out by analog circuits; weight storage,
control and communication are implemented by digital
circuits. By emulating the neuron and synapse differential
equations with analog circuits, power consumption can
be reduced by several orders of magnitude, compared
with solving the differential equations numerically using
digital processors [282].
3) System Architecture
In order to address the high communication throughput
required by massive simulation and high acceleration
factor, HICANN adopts a unique technique, namely wafer-scale
integration. The wafer is not cut into individual
chips, but all the chips on the wafer are directly interconnected
to provide high connection density [283]. A wafer
consists of 56 reticles, each of which consist of 8 analog
network chips (ANC) [283]. The major component of ANC
is Analog Neural Network Core (ANNCORE), which contains
128k synapses and 512 membrane circuits/dendrite
membrane (DenMem) circuits [283]. Each DenMem circuit
is connected to 224 synapses. Multiple DenMem circuits
can be grouped together to build a neuron, such that
neurons can have a variable number of synapses [280].
Up to 64 DemMem circuits can be grouped together, resulting
in a single neuron with 14336 synapses. Each synapse
has a 4-bit weight stored in SRAM. Synapse current
is generated by DAC.
The fault tolerant nature of biological neural network
is preserved by HICANN, and hierarchical programmable
topology enables the replacement of individual defect
neurons or an entire neuron core.
The communication in BrainScales has a hierarchical
architecture. The Layer-1 communication is carried out
by a continuous-time serial bus system that enables inter
wafer communication between ANCs across the entire
wafer. The 521 wires of the Layer-1 bus form 256 differential
lanes connected directly to the ANCs. Since the signal
has to travel along horizon and vertical buses across the
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