IEEE Circuits and Systems Magazine - Q2 2022 - 24

Neural Network (SNN) model. The axon block in the FCore
is to memorize the historical spikes or ANN inputs and feed
them through connected synapses according to its configuration
mode. After receiving signals from synapses, the dendrites
block performs either integration (SNN mode) or MAC
(multiplication and accumulation) operation (ANN mode).
The shared dendrites then deliver the results to soma block.
As shown in Equation 23, in SNN mode, the Tianjic chip
adopts the leaky Integrate-and-fire (LIF) model, where V(t)
denotes the membrane potential in the soma unit. The soma
part receives voltage VR
coming from dendrites, here Vr1
the reset voltage and x is the time constant.
()
x
dVt
t
d
i
=- -+ Rir1
6Vt VV
()
@
is
(23)
2) Hardware Platform
The Tianjic chip is fabricated with 28 nm high performance
low power (HLP) process, and it occupies 3.8 × 3.8 mm2
die area. One Tianjic chip consists of 156 Fcores. For
each Fcore, Tianjic chip supports 32 weight indices and
256 fan-ins/fan-outs (N), and the static random-access
memory (SRAM) of each Fcores is around 22 KB. Unlike
Lohi and TrueNorth, the Tianjic chip adopts synchronous
circuits and its clock frequency is 300 MHz. The average
power consumption for control, audio and base applications
is 400 mW under 0.9 V working voltage. Generally,
the Tianjic chip requires 5,050 clock periods to complete
a round of computations and communications.
3) Architecture
As discussed in the previous section, Tianjic embraces a
2D mesh many-core architecture to achieve massive parallelism.
At the coarse-grained level, developers are able
to assign some Fcores to ANN mode and other Fcores to
SNN mode concurrently. While at the Fcore block (finegrained)
level, the independently reconfigurable axon and
soma enable Tianjic to implement neuromorphic and artificial
neural networks. Tianjic chip also supports transition
mode between ANN and SNN, that is, when axon and
soma are set to different modes, FCore can process the
ANN's input in axon block to SNN's output in soma block
or receive the SNN's inputs from the axon block and convert
them to the ANN's outputs in the soma block. This
unique transition mode is hybrid mode.
There are two chunks of Axon memory. When the Axon
is assigned to ANN mode, the two chunks are served as
a ping pong buffer for ANN's input. In SNN mode, these
two chunks are merged to store the temporal spike patterns
in a time window. As for the dendrite block, the
processing neurons are divided into groups, each group
has 24-bit accumulators to support the vector-matrix
multiplication (VMM) that can be used in both ANN and
SNN modes. The dataflow in the soma block is different
24
IEEE CIRCUITS AND SYSTEMS MAGAZINE
in ANN mode and SNN mode: In ANN mode, data flows in
'bias, activation function, output transmission' fashion,
and the biased activation value is 25-bit; The dataflow
changes to 'potential leakage, spike generation, output
transmission' fashion in SNN mode, where the membrane
potential is also 25-bit.
4) Communication
The routing packet format is the same for both SNN and
ANN interFcore transmission, which consists of control,
address, and data segments. The post synaptic axon parses
received ANN or SNN signals from soma and renders
them to the routing blocks. In ANN mode, the data segment
transmits as 8-bit activation while in SNN mode it
transmits as nothing (itself is a spike or none). The 1KB
routing LUT consisting of address and control segments
will route the packet to one of the 5 communication channels:
local, eastern, western, southern, and northern.
Tianjic chip adopts conventional P2P [114] routing
scheme and adjacent multicast (AMC) routing scheme.
The reconfigurable routing table allows each Fcore to
connect with any other neuron.
5) Supporting Software/Software Ecosystem
Tianjic's software tool chain supports the deployment of
various SNN and ANN models. To reduce the latency of
the application, Tianjic developed several software techniques,
including but not limited to unified abstraction
for programming and an automatic compiler for mapping
hardware. The software tool chain also supports direct
training and indirect training for neural networks. The direct
training deploys a spatiotemporal back-propagation
algorithm to train the network on chip. The indirect training
uses a trained ANN and converts it to SNN.
6) Applications
Tianjic has been tested for several computer vision tasks,
such as MNIST detection. To demonstrate that one Tianjic
chip can handle complex biological plausible neural
networks in parallel, The Tianjic team designed an unmanned
bicycle experiment. The experiment requires the
chip to handle obstacle avoidance, real-time object detection,
voice recognition and decision-making with different
neural networks. For example, SNN is utilized for voice
recognition, CNN is used for object detection and CANN
[297] is used for target tracking.
In addition to the aforementioned systems, many other
large-scale neuromorphic computing platforms have
been playing an important role in machine intelligence
and computational neuroscience. Table III provides a
more comprehensive comparison of the technology and
performance of the large-scale neuromorphic systems
that are currently active.
SECOND QUARTER 2022
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