IEEE Circuits and Systems Magazine - Q2 2022 - 32

[165] A. Yousefzadeh, T. Masquelier, T. Serrano-Gotarredona, and
B. Linares-Barranco, " Hardware implementation of convolutional STDP
for on-line visual feature learning, " in Proc. IEEE Int. Symp. Circuits Syst.
(ISCAS), 2017, pp. 1-4.
[166] A. Yousefzadeh, E. Stromatias, M. Soto, T. Serrano-Gotarredona,
and B. Linares-Barranco, " On practical issues for stochastic STDP hardware
with 1-bit synaptic weights, " Front. Neurosci., vol. 12, p. 665, 2018,
doi: 10.3389/fnins.2018.00665.
[167] C. Bartolozzi, O. Nikolayeva, and G. Indiveri, " Implementing homeostatic
plasticity in VLSI networks of spiking neurons, " in Proc. 15th
IEEE Int. Conf. Electron., Circuits Syst., 2008, pp. 682-685, doi: 10.1109/
ICECS.2008.4674945.
[168] J. Schreiter, U. Ramacher, A. Heittmann, D. Matolini, and R. Schuffny,
" Analog implementation for networks of integrate-and-fire neurons
with adaptive local connectivity, " in Proc. 12th IEEE Workshop on Neural
Netw. Signal Process., 2002, pp. 657-666.
[169] F. L. M. Huayaney, S. Nease, and E. Chicca, " Learning in silicon
beyond STDP: A neuromorphic implementation of multi-factor synaptic
plasticity with calcium-based dynamics, " IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 63, pp. 2189-2199, 2016, doi: 10.1109/TCSI.
2016.2616169.
[170] Y. Meng, K. Zhou, J. J. C. Monzon, and C.-S. Poon, " Iono-neuromorphic
implementation of spike-timing-dependent synaptic plasticity, " in
Proc. Annu. Int. Conf. IEEE Eng. Med. Biol. Soc., 2011, pp. 7274-7277.
[171] L. Alvado, J. Tomas, S. R.-L. Masson, and V. Douence, " Design of an
analogue ASIC using subthreshold CMOS transistors to model biological
neurons, " in Proc. IEEE 2001 Custom Integr. Circuits Conf., 2001, pp.
97-100.
[172] C. Bartolozzi, S. Mitra, and G. Indiveri, " An ultra low power current-mode
filter for neuromorphic systems and biomedical signal processing, "
in Proc. IEEE Biomed. Circuits Syst. Conf., 2006, pp. 130-133.
[173] J. Georgiou, E. M. Drakakis, C. Toumazou, and P. Premanoj, " An
analogue micropower log-domain silicon circuit for the Hodgkin and
Huxley nerve axon, " in Proc. IEEE Int. Symp. Circuits Syst. VLSI, 1999,
vol. 2, pp. 286-289.
[174] K. Nakada, T. Asai, T. Hirose, and Y. Amemiya, " Analog CMOS implementation
of a neuromorphic oscillator with current-mode low-pass
filters, " in Proc. IEEE Int. Symp. Circuits Syst., 2005, pp. 1923-1926.
[175] K. I. Papadimitriou, S.-C. Liu, G. Indiveri, and E. M. Drakakis, " Neuromorphic
log-domain silicon synapse circuits obey Bernoulli dynamics:
A unifying tutorial analysis, " Front. Neurosci., vol. 8, p. 428, 2015, doi:
10.3389/fnins.2014.00428.
[176] T. Yu and G. Cauwenberghs, " Analog VLSI biophysical neurons
and synapses with programmable membrane channel kinetics, " IEEE
Trans. Biomed. Circuits Syst., vol. 4, pp. 139-148, 2010, doi: 10.1109/
TBCAS.2010.2048566.
[177] J. Binas, G. Indiveri, and M. Pfeiffer, " Spiking analog VLSI neuron
assemblies as constraint satisfaction problem solvers, " in Proc. IEEE
Int. Symp. Circuits Syst. (ISCAS), 2016, pp. 2094-2097.
[178] C.-H. Chien, S.-C. Liu, and A. Steimer, " A neuromorphic VLSI circuit
for spike-based random sampling, " IEEE Trans. Emerg. Topics Comput.,
vol. 6, pp. 135-144, 2015, doi: 10.1109/TETC.2015.2424593.
[179] J. Fieres, J. Schemmel, and K. Meier, " Realizing biological spiking
network models in a configurable wafer-scale hardware system, "
in Proc. IEEE Int. Joint Conf. Neural Netw. (IEEE World Congr. Comput.
Intell.), 2008, pp. 969-976.
[180] D. H. Goldberg, G. Cauwenberghs, and A. G. Andreou, " Analog
VLSI spiking neural network with address domain probabilistic synapses, "
in Proc. ISCAS 2001. IEEE Int. Symp. Circuits Syst., 2001, vol. 3,
pp. 241-244.
[181] F. Grassia, T. Lévi, J. Tomas, S. Renaud, and S. Saïghi, " A neuromimetic
spiking neural network for simulating cortical circuits, " in Proc.
45th Annu. Conf. Inf. Sci. Syst., 2011, pp. 1-6.
[182] E. Neftci, J. Binas, U. Rutishauser, E. Chicca, G. Indiveri, and R.
J. Douglas, " Synthesizing cognition in neuromorphic electronic systems, "
Proc. Nat. Acad. Sci., vol. 110, pp. E3468-E3476, 2013, doi: 10.1073/
pnas.1212083110.
[183] D. Querlioz and V. Trauchessec, " Stochastic resonance in an analog
current-mode neuromorphic circuit, " in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS2013), 2013, pp. 1596-1599.
[184] S. Renaud, J. Tomas, Y. Bornat, A. Daouzli, and S. Saïghi, " Neuromimetic
ICs with analog cores: an alternative for simulating spiking neural
networks, " in Proc. IEEE Int. Symp. Circuits Syst., 2007, pp. 3355-3358,
doi: 10.1109/ISCAS.2007.378286.
32
IEEE CIRCUITS AND SYSTEMS MAGAZINE
[185] A. Utagawa, T. Asai, T. Hirose, and Y. Amemiya, " An inhibitory
neural-network circuit exhibiting noise shaping with subthreshold MOS
neuron circuits, " IEICE Trans. Fund. Electron., Commun. Comput. Sci.,
vol. 90, pp. 2108-2115, 2007, doi: 10.1093/ietfec/e90-a.10.2108.
[186] Y. Wang and S.-C. Liu, " Programmable synaptic weights for an
aVLSI network of spiking neurons, " in Proc. IEEE Int. Symp. Circuits Syst.,
2006, p. 4, doi: 10.1109/ISCAS.2006.1693637.
[187] Y. Wang and S.-C. Liu, " Input evoked nonlinearities in silicon dendritic
circuits, " in Proc. IEEE Int. Symp. Circuits Syst., 2009, pp. 2894-
2897, doi: 10.1109/ISCAS.2009.5118407.
[188] L. Zhang, Q. Lai, and Y. Chen, " Configurable neural phase shifter
with spike-timing-dependent plasticity, " IEEE Electron Device Lett., vol.
31, pp. 716-718, 2010, doi: 10.1109/LED.2010.2049558.
[189] C. Zhao, J. Li, L. Liu, L. S. Koutha, J. Liu, and Y. Yi, " Novel spike
based reservoir node design with high performance spike delay loop, "
in Proc. 3rd ACM Int. Conf. Nanoscale Comput. Commun., 2016, pp. 1-5.
[190] A. Ghani, T. M. McGinnity, L. P. Maguire, and J. Harkin, " Area efficient
architecture for large scale implementation of biologically plausible
spiking neural networks on reconfigurable hardware, " in Proc. Int.
Conf. Field Programmable Logic Appl., 2006, pp. 1-2.
[191] M. Giulioni, X. Lagorce, F. Galluppi, and R. B. Benosman,
" Event-based computation of motion flow on a neuromorphic analog
neural platform, " Front. Neurosci., vol. 10, p. 35, 2016, doi: 10.3389/
fnins.2016.00035.
[192] M. Giulioni, F. Corradi, V. Dante, and P. D. Giudice, " Real time unsupervised
learning of visual stimuli in neuromorphic VLSI systems, " Sci.
Rep., vol. 5, p. 14730, 2015.
[193] P. Camilleri et al., " A neuromorphic a VLSI network chip with configurable
plastic synapses, " in Proc. 7th Int. Conf. Hybrid Intell. Syst. (HIS
2007), 2007, pp. 296-301, doi: 10.1109/ICHIS.2007.4344067.
[194] M. Giulioni et al., " A VLSI network of spiking neurons with plastic
fully configurable " stop-learning " synapses, " in Proc. 15th IEEE
Int. Conf. Electron., Circuits Syst., 2008, pp. 678-681, doi: 10.1109/
ICECS.2008.4674944.
[195] M. Giulioni, M. Pannunzi, D. Badoni, V. Dante, and P. D. Giudice,
" Classification of correlated patterns with a configurable analog
VLSI neural network of spiking neurons and self-regulating plastic
synapses, " Neural Comput., vol. 21, pp. 3106-3129, 2009, doi: 10.1162/
neco.2009.08-07-599.
[196] Q. Sun, F. Schwartz, J. Michel, Y. Herve, and R. D. Molin, " Implementation
study of an analog spiking neural network for assisting
cardiac delay prediction in a cardiac resynchronization therapy device, "
IEEE Trans. Neural Netw., vol. 22, pp. 858-869, 2011, doi: 10.1109/
TNN.2011.2125986.
[197] P. Hafliger, " Adaptive WTA with an analog VLSI neuromorphic
learning chip, " IEEE Trans. Neural Netw., vol. 18, pp. 551-572, 2007, doi:
10.1109/TNN.2006.884676.
[198] H.-Y. Hsieh and K.-T. Tang, " Hardware friendly probabilistic spiking
neural network with long-term and short-term plasticity, " IEEE
Trans. Neural Netw. Learn. Syst., vol. 24, pp. 2063-2074, 2013.
[199] F. Grassia, L. Buhry, T. Lévi, J. Tomas, A. Destexhe, and S. Saïghi,
" Tunable neuromimetic integrated system for emulating cortical neuron
models, " Front. Neurosci., vol. 5, p. 134, 2011, doi: 10.3389/fnins.
2011.00134.
[200] F. L. M. Huayaney and E. Chicca, " A VLSI implementation of a calcium-based
plasticity learning model, " in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), 2016, pp. 373-376.
[201] J. Park, M.-W. Kwon, H. Kim, and B.-G. Park, " Neuromorphic system
based on CMOS inverters and Si-based synaptic device, " J. Nanosci.
Nanotechnol., vol. 16, pp. 4709-4712, 2016, doi: 10.1166/jnn.2016.12234.
[202] S. Saighi, J. Tomas, Y. Bornat, B. Belhadj, O. Malot, and S. Renaud,
" Real-time multi-board architecture for analog spiking neural networks, "
in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 1939-1942, doi:
10.1109/ISCAS.2010.5538039.
[203] S. Millner, A. Hartel, J. Schemmel, and K. Meier, " Towards biologically
realistic multi-compartment neuron model emulation in analog
VLSI, " in Proc. ESANN, 2012.
[204] G. Rovere, Q. Ning, C. Bartolozzi, and G. Indiveri, " Ultra low leakage
synaptic scaling circuits for implementing homeostatic plasticity
in neuromorphic architectures, " in Proc. IEEE Int. Symp. Circuits Syst.
(ISCAS), 2014, pp. 2073-2076.
[205] S. Saighi, J. Tomas, Y. Bornat, and S. Renaud, " A conductancebased
silicon neuron with dynamically tunable model parameters, " in
Conf. Proc. 2nd Int. IEEE EMBS Conf. Neural Eng., 2005, pp. 285-288.
SECOND QUARTER 2022
IEEE Circuits and Systems Magazine - Q2 2022

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2022
