IEEE Circuits and Systems Magazine - Q2 2022 - 33

[206] S. Saighi, Y. Bornat, J. Tomas, and S. Renaud, " Neuromimetic ICs
and system for parameters extraction in biological neuron models, "
in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 4207-4210, doi: 10.1109/
ISCAS.2006.1693557.
[207] S. Saighi, Y. Bornat, J. Tomas, G. L. Masson, and S. Renaud, " A
library of analog operators based on the Hodgkin-Huxley formalism for
the design of tunable, real-time, silicon neurons, " IEEE Trans. Biomed.
Circuits Syst., vol. 5, pp. 3-19, 2010, doi: 10.1109/TBCAS.2010.2078816.
[208] T. Yu and G. Cauwenberghs, " Analog VLSI neuromorphic network
with programmable membrane channel kinetics, " in Proc. IEEE
Int. Symp. Circuits Syst., 2009, pp. 349-352, doi: 10.1109/ISCAS.2009.
5117757.
[209] T. Yu, T. J. Sejnowski, and G. Cauwenberghs, " Biophysical neural
spiking, bursting, and excitability dynamics in reconfigurable analog
VLSI, " IEEE Trans. Biomed. Circuits Syst., vol. 5, pp. 420-429, 2011, doi:
10.1109/TBCAS.2011.2169794.
[210] B. Marr and J. Hasler, " Compiling probabilistic, bio-inspired circuits
on a field programmable analog array, " Front. Neurosci., vol. 8,
p. 86, 2014, doi: 10.3389/fnins.2014.00086.
[211] B. McGinley, P. Rocke, F. Morgan, and J. Maher, " Reconfigurable
analogue hardware evolution of adaptive spiking neural network controllers, "
in Proc. 10th Annu. Conf. Genetic Evolutionary Comput., 2008,
pp. 289-290, doi: 10.1145/1389095.1389143.
[212] P. Rocke, B. McGinley, J. Maher, F. Morgan, and J. Harkin, " Investigating
the suitability of FPAAs for evolved hardware spiking neural
networks, " in Proc. Int. Conf. Evolvable Syst., 2008, pp. 118-129.
[213] J. Zhao and Y.-B. Kim, " Circuit implementation of Fitzhugh-Nagumo
neuron model using field programmable analog arrays, " in Proc.
50th Midwest Symp. Circuits Syst., 2007, pp. 772-775.
[214] S. Nease, S. George, P. Hasler, S. Koziol, and S. Brink, " Modeling
and implementation of voltage-mode CMOS dendrites on a reconfigurable
analog platform, " IEEE Trans. Biomed. Circuits Syst., vol. 6, pp.
76-84, 2011, doi: 10.1109/TBCAS.2011.2163714.
[215] E. Farquhar, C. Gordon, and P. Hasler, " A field programmable neural
array, " in Proc. IEEE Int. Symp. Circuits Syst., 2006, pp. 4114-4117.
[216] M. Liu, H. Yu, and W. Wang, " FPAA based on integration of CMOS
and nanojunction devices for neuromorphic applications, " in Proc. Int.
Conf. Nano-Netw., 2008, pp. 44-48.
[217] M. R. Azghadi, S. Moradi, and G. Indiveri, " Programmable neuromorphic
circuits for spike-based neural dynamics, " in Proc. IEEE
11th Int. New Circuits Syst. Conf. (NEWCAS), 2013, pp. 1-4, doi: 10.1109/
NEWCAS.2013.6573600.
[218] F. Corradi, H. You, M. Giulioni, and G. Indiveri, " Decision making
and perceptual bistability in spike-based neuromorphic VLSI systems, "
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2015, pp. 2708-2711, doi:
10.1109/ISCAS.2015.7169245.
[219] M. A. Petrovici et al., " Characterization and compensation of
network-level anomalies in mixed-signal neuromorphic modeling platforms, "
PloS One, vol. 9, no. 10, p. e108590, 2014, doi: 10.1371/journal.
pone.0108590.
[220] H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, " A unified
synapse-neuron building block for hybrid VLSI neural networks, " in
Proc. IEEE Int. Symp. Circuits Syst.(ISCAS 96), 1996, vol. 3, pp. 483-486.
[221] S. Mitra, G. Indiveri, and S. Fusi, " Learning to classify complex patterns
using a VLSI network of spiking neurons, " in Advances in Neural
Information Processing Systems, J. Platt, D. Koller, Y. Singer, and S. Roweis,
Eds. Curran Associates, Inc., 2008, vol. 20.
[222] J. V. Arthur and K. Boahen, " Learning in silicon: Timing is everything, "
in Proc. Adv. Neural Inf. Process. Syst., 2006, pp. 75-82.
[223] J. M. Cruz-Albrecht, M. W. Yung, and N. Srinivasa, " Energy-efficient
neuron, synapse and STDP integrated circuits, " IEEE Trans. Biomed. Circuits
Syst., vol. 6, pp. 246-256, 2012, doi: 10.1109/TBCAS.2011.2174152.
[224] S. Hussain, A. Basu, M. Wang, and T. J. Hamilton, " DELTRON: Neuromorphic
architectures for delay based learning, " in Proc. IEEE Asia
Pacific Conf. Circuits Syst., 2012, pp. 304-307.
[225] L. Alvado, S. Saïghi, J. Tomas, and S. Renaud, " An exponential-decay
synapse integrated circuit for bio-inspired neural networks, " in Proc.
Int. Work-Conf. Artif. Neural Netw. Springer-Verlag, 2003, pp. 670-677.
[226] S. R. Deiss, R. J. Douglas, A. M. Whatley, and W. Maass, " A pulsecoded
communications infrastructure for neuromorphic systems, "
Proc. Pulsed Neural Netw., 1999, pp. 157-178.
[227] F. Sargeni and V. Bonaiuto, " An interconnection architecture for
integrate and fire neuromorphic multi-chip networks, " in Proc. 52nd
IEEE Int. Midwest Symp. Circuits Syst., 2009, pp. 877-880.
SECOND QUARTER 2022
[228] A. Cassidy, T. Murray, A. G. Andreou, and J. Georgiou, " Evaluating
on-chip interconnects for low operating frequency silicon neuron arrays, "
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2011, pp. 2437-2440.
[229] D. Vainbrand and R. Ginosar, " Scalable network-on-chip architecture
for configurable neural networks, " Microprocessors Microsyst., vol.
35, pp. 152-166, 2011, doi: 10.1016/j.micpro.2010.08.005.
[230] S. Pande et al., " Fixed latency on-chip interconnect for hardware
spiking neural network architectures, " Parallel Comput., vol. 39, pp.
357-371, 2013, doi: 10.1016/j.parco.2013.04.010.
[231] Y. Suzuki and L. E. Atlas, " A study of regular architectures for digital
implementation of neural networks, " in Proc. IEEE Int. Symp. Circuits
Syst., 1989, pp. 82-85.
[232] A. Mortara and E. A. Vittoz, " A communication architecture tailored
for analog VLSI artificial neural networks: Intrinsic performance
and limitations, " IEEE Trans. Neural Netw., vol. 5, pp. 459-466, 1994, doi:
10.1109/72.286916.
[233] A. Mortara, E. A. Vittoz, and P. Venier, " A communication scheme
for analog VLSI perceptive systems, " IEEE J. Solid-State Circuits, vol. 30,
pp. 660-669, 1995, doi: 10.1109/4.387069.
[234] P. Merolla, J. Arthur, R. Alvarez, J.-M. Bussat, and K. Boahen, " A
multicast tree router for multichip neuromorphic systems, " IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 61, pp. 820-833, 2013, doi: 10.1109/
TCSI.2013.2284184.
[235] P. A. Merolla, J. V. Arthur, B. E. Shi, and K. A. Boahen, " Expandable
networks for neuromorphic chips, " IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 54, pp. 301-311, 2007, doi: 10.1109/TCSI.2006.887474.
[236] S.-C. Liu, T. Delbruck, G. Indiveri, A. Whatley, and R. Douglas,
Event-Based Neuromorphic Systems. Wiley, 2014.
[237] M. Jabłon´ski, T. Serrano-Gotarredona, and B. Linares-Barranco,
" High-speed serial interfaces for event-driven neuromorphic systems, "
in Proc. Int. Conf. Event-based Control, Commun., Signal Process.
(EBCCSP), 2015, pp. 1-4, doi: 10.1109/EBCCSP.2015.7300697.
[238] S. Ramakrishnan, R. Wunderlich, J. Hasler, and S. George, " Neuron
array with plastic synapses and programmable dendrites, " IEEE
Trans. Biomed. Circuits Syst., vol. 7, pp. 631-642, 2013, doi: 10.1109/
TBCAS.2013.2282616.
[239] C. Zamarreño-Ramos, A. Linares-Barranco, T. Serrano-Gotarredona,
and B. Linares-Barranco, " Multicasting mesh AER: A scalable
assembly approach for reconfigurable neuromorphic structured AER
systems. Application to ConvNets, " IEEE Trans. Biomed. Circuits Syst.,
vol. 7, pp. 82-102, 2012, doi: 10.1109/TBCAS.2012.2195725.
[240] E. Chicca, A. M. Whatley, P. Lichtsteiner, V. Dante, T. Delbruck, P.
D. Giudice, R. J. Douglas, and G. Indiveri, " A multichip pulse-based neuromorphic
infrastructure and its application to a model of orientation
selectivity, " IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp. 981-993,
2007, doi: 10.1109/TCSI.2007.893509.
[241] R. Paz-Vicente et al., " PCI-AER interface for neuro-inspired spiking
systems, " in Proc. IEEE Int. Symp. Circuits Syst., 2006, p. 4, doi: 10.1109/
ISCAS.2006.1693296.
[242] V. Thanasoulis, J. Partzsch, S. Hartmann, C. Mayr, and R.
Schüffny, " Dedicated FPGA communication architecture and design
for a large-scale neuromorphic system, " in Proc. 19th IEEE Int. Conf.
Electron., Circuits, Syst. (ICECS 2012), 2012, pp. 877-880, doi: 10.1109/
ICECS.2012.6463548.
[243] V. Thanasoulis, B. Vogginger, J. Partzsch, and R. Schüffny, " A
pulse communication flow ready for accelerated neuromorphic experiments, "
in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2014, pp. 265-268,
doi: 10.1109/ISCAS.2014.6865116.
[244] S. Scholze et al., " A 32 GBit/s communication SoC for a waferscale
neuromorphic system, " Integration, vol. 45, pp. 61-75, 2012, doi:
10.1016/j.vlsi.2011.05.003.
[245] T. Sharp, C. Patterson, and S. Furber, " Distributed configuration of
massively-parallel simulation on Spinnaker neuromorphic hardware, "
in Proc. Int. Joint Conf. Neural Netw., 2011, pp. 1099-1105.
[246] D. Brüderl et al., " A comprehensive workflow for general-purpose
neural modeling with highly configurable neuromorphic hardware systems, "
Biol. Cybern., vol. 104, pp. 263-296, 2011, doi: 10.1007/s00422-011
-0435-9.
[247] F. Galluppi, S. Davies, S. Furber, T. Stewart, and C. Eliasmith, " Real
time on-chip implementation of dynamical systems with spiking neurons, "
in Proc. Int. Joint Conf. Neural Netw. (IJCNN), 2012, pp. 1-8.
[248] F. Galluppi, S. Davies, A. Rast, T. Sharp, L. A. Plana, and S. Furber,
" A hierachical configuration system for a massively parallel neural
hardware platform, " in Proc. 9th Conf. Comput. Front., 2012, pp. 183-192.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
33
IEEE Circuits and Systems Magazine - Q2 2022

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q2 2022
