IEEE Circuits and Systems Magazine - Q4 2022 - 11

with realizing large delay compensation with fine
resolution at different domains in the receiver chain.
Section IV discusses the fast beam-training algorithm
and practical design considerations for analog PAAs
leveraging TTD SSP architecture. Section V will present
the hardware implementation of reconfigurable
time delay units enabling different SSP modes along
with hardware validation methods for wideband
PAAs. Section VI presents future works expanding
the proposed TTD-based PAAs for beam-training with
planar arrays, multiple access applications, and standardization
of wireless protocols. Section VII concludes
this article.
III. Overview of mmW TTD PAAs
This section describes the possible architectural
choices for TTD PAAs. The design of PAAs are based
on two principles: (1) phase/delay alignment of signals
either in transmit or receive path, and (2) summation
of phase/delay aligned signals. To align the received
signals in a PAA, delay elements should provide the
proper delay to each received signal. The delay can be
applied to the signal in mmW, LO, baseband, or digital
domains. When the fractional bandwidth of the signal
or the required delay range in the phased array system
is small, the delay is approximated by a phase shift as
discussed before. There are different topologies that
are common in the implementation of PAA transceivers
(Fig. 8) such as RF phase shifting [62]-[65], LO phase
shifting [66], [67], baseband (BB) phase shifting [68],
[69], and digital phase shifting [70]. In the RF phaseshifting
architecture, after applying the required phase
shift in each RF path, the signals can be combined
together. LO phase shifting architecture uses the PS in
the LO port of the mixer. In BB and digital phase-shifting
architecture, the received signals are aligned after
downconversion, using analog circuitry in baseband or
in a digital processor. Either of these architectures is a
good candidate when the signal's fractional bandwidth
is small, or the required delay range in the PAA is small.
For large delay-bandwidth product cases, delay
units are necessary to prevent beam squint. Similar
to a PS-based PAAs, the location of the time delay
unit makes possible multiple architectures ( mmW/RF
path, LO port of the mixer, BB, or digital domains). In
the mmW/RF TTD architecture, the time delay unit is
placed in the mmW/RF domain before downconversion.
The received signals at each receiver path can be combined
constructively, as shown in Fig. 8(a). The mixer
is shared between multiple paths and only one LO
signal is necessary which allows significant area and
power reduction. As the signals are combined before
Fourth quartEr 2022
downconversion, interferers are removed due to spatial
filtering, which reduces the linearity requirements
of the blocks after the combiner. Although there are
different implementations of the mmW/RF TTD-based
PAAs, these implementations occupy a large area on
the chip and there are serious limitations on the delay
range. Table 1 highlights the integrated mmW/RF TTD
implementations over the past decade starting with
the seminal work [71] by Chu and Hashemi in 2007.
Placing the TTD element in the LO path of the mixer
does not resolve these limitations especially when
handling wideband range One may wonder whether
it's possible to place TTD block in the LO path. Since
the LO signal is a single tone, the time delay can be
replaced as a phase shift which can further be moved
to either RF, or BB side mathematically. However, this
scenario is identical to compensating a wideband signal
using the phase shift, eventually, introducing beam
squint at band edges. Therefore, the LO TTD approach
does not resolve these limitations when handling wideband
range. Digital TTD PAA is the same as a digital
phased array and the challenges are the same such
as high power consumption including the need for
highly linear analog-to-digital converter (ADC) as well
as other linear elements. However, there are promising
TTDbased PAAs in BB with large delay-bandwidth
products [22], [72]. Table 2 highlights recent SOTA
TTD-based PAAs and delay lines implemented at BB.
Figure 8. different
receiver architectures for delay-sum
beamforming (a) mmW, (b) Lo, (c) Baseband, and (d) digital
domains.
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