IEEE Circuits and Systems Magazine - Q4 2022 - 12

In an array with BB TTD elements as shown in Fig. 9
[22], instead of delaying the down-converted and phase
shifted signals from the antennas followed by sampling
and digitization, the signals are sampled at different time
instants. Thus, the complexity of delaying signals is shifted
to the clock path where precise and calibrated delays can
be applied in the advanced semiconductor technology
nodes. More importantly, a large delay range-to-resolution
ratio can be easily realized while supporting a relatively
larger number of antennas and bandwidth. The switchedcapacitor
adder based implementation requires multiple
time-interleaved and delay compensated phases for formation
of the beam [22]. In the sampling phase, the input
signal from each channel is first sampled (with delayed
time-interleaved clocks) on a sampling capacitor. After the
last sampling phase, the stored charges on each capacitor
corresponding to each channel (and each timeinterleaved
phase) are summed to form the beam. However, since time
delay in BB is not mathematically equivalent to the time
delay in the RF domain, a small phase shift is still necessary
[20], [22]. For example, if a time delay of τd is needed,
it can be implemented in the BB with a time delay equal to
τd plus a phase shift equal to
LO d [20], [22], [37]. The
BB TTD architecture shown in Fig. 9 is hereby referred as
discrete-time TTD SSP.
A PS can be implemented in the RF, LO, BB, or digital
domain to provide the required phase shift to the
BB time delay units. The mmW/RF PS can be limited by
the maximum delay-bandwidth product of the receiver.
Table 1.
Survey of TTD implementations at RF/mmW.
Digital implementation of the TTD or PS is similar to digital
phaseshifting architecture with each RF path requiring
an ADC which increases the power consumption of
the whole system considerably. ADCs should be linear
enough to tolerate the large interferences which further
increases the whole system's power consumption. Placing
a PS in BB or LO is another feasible option (Fig. 9). In
these architectures, each RF path has a dedicated mixer
and an LO signal. PS in the LO port of the mixer should
operate at the LO frequency. However, the PS in the BB
or intermediate frequencies has to operate at lower frequencies.
Though the loss and phase error of the PS in
RF frequencies is higher than the PS at BB, the PS at
the BB has to operate at a much higher fractional bandwidth
while the PS in LO path only deals with a single
tone signal (Fig. 9(a)). The PS can be implemented in the
LO [73] as well as conventional PS architectures.
BB PS using vector summation is also another option.
Vector summing PS is based on the weighted summation
of quadrature signals. Quadrature signal generation is
possible using a quadrature coupler, polyphase filters,
or using quadrature mixers. Quadrature couplers at the
BB occupies a large chip area and thus less preferred.
Polyphase filters usually are narrow-band which contradicts
with the large-delay bandwidth required. The use
of quadrature downconversion mixers is another option
though at the expense of routing complexities.
The next section presents the framework of leveraging
discrete-time TTD SSP for fast beam-training
TTD Method
JSSCC'07 [12]
LC Delay
# of FE Elements
# of Beams
Domain
Freq.(GHz)
Bandwidhth (MHz)
Delay Range/Resolution
(ps)
Area (mm2)
Power (mW)
IC technology
12
4
1
RF
8
18000
300/15
9.9
560
CMOS (130)
IEEE cIrcuIts and systEms magazInE
COMM' 08 [13]
LC Delay
2 × 2
49
RF
8
15000
1750/150
16.8
945
CMOS (130)
TMTT' 13 [14]
LC Delay
6
7
RF
35
10000
/10
5.1
825
BiCMOS (130)
IMS' 15 [16]
LC Delay
-
-
RF
1~20
19000
400/5
4
6
CMOS (130)
RFIC' 18 [17]
LC Delay
-
-
RF
2~20
18000
508/4
5.45
285
BiCMOS (130)
Fourth quartEr 2022
IEEE Circuits and Systems Magazine - Q4 2022

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