IEEE Circuits and Systems Magazine - Q4 2022 - 17

discretetime TTD SSP shown in Fig. 9 applied to both the
data communications as well as beam-training SSP modes.
A. Important Sub-Systems in Discrete-Time TTD SSP
The analog array though more energy efficient when
compared to hybrid TTD and digital arrays [51] require
larger unity-gain bandwidth amplifiers to have similar
performance. The circuit performance is further
constrained with the parasitic capacitance, routing
losses, crosstalk, and any possible mismatches during
fabrication evident at multiple levels including silicon,
packaging, or printed circuit board. Design considerations
for the key blocks are described here to ensure
low-power consumption is upheld for analog arrays as
compared to hybrid or digital TTD SSP [51] including its
ability to achieve fractional delays with high precision.
This section presents design considerations for the key
design blocks: (i) sample-and-hold, (ii) wideband signal
combiners, and (iii) precision clock generation. Fig. 16
shows a more detailed illustration of the discrete-time
TTD SSP. The circuit design consideration to support
rainbow beam training lies in determining the minimum
number of interleaving level that is required to achieve
a certain delay. For a critically spaced linear N element
array, λ/2 spacing, and an antenna system with a
diversity factor of unity, we derive the minimum interleaving
level, denoted as MBT, and express as:
MN
BT t12 1
(14)
As observed, the required levels increase linearly
with the number of antennas, leading to the inclusion of
more samplers which comprise of high linearity switches
and capacitors in the design. Interested readers can refer
to [22], [26], [51], [52] for further understanding.
1. Sample-and-Hold: The
design constraints
for
the input sample-and-hold draws parallel to the
design requirements of a high-speed time-interleaved
ADC [78]. Different interleaver configurations
can be analyzed based on a simplified switch
model in which the switch resistance and capacitance
are linked to the technology. To reduce
effect of sampling jitter, it is preferable to sample
first followed by subsampling however at the cost
of additional source followers which can significantly
impact power consumption and linearity.
To relax the power consumption, the first sampler
can be interleaved (typically by 2 or 4) at the cost
of slightly higher mismatch and jitter [79].
2. Signal Combiners: The signal combiner is a critical
component for wideband discrete-time beamforming
that requires careful design considerations
of several parameters including gain, bandwidth,
number of summing channels (each channel refers
Fourth quartEr 2022
Figure 15. comparison between ttd algorithms and Paabased
beam sweeping in terms of the aoa rmsE at different
distances between the Bs and uE.
to a downconverted RF signal from each antenna
element), dynamic range, and power consumption.
The multi-parameter optimization considering the
required design specifications for each system can
Figure 14. PaPr comparison between proposed and fully
loaded oFdm waveforms, assuming BPsK or qPsK symbols.
Figure 16. generic ttd ssP architecture.
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IEEE Circuits and Systems Magazine - Q4 2022

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