IEEE Circuits and Systems Magazine - Q4 2022 - 18

be addressed using either a closed-loop or openloop
summing amplifiers, shown in Fig. 17(a). In [22],
a closed-loop operational transconductance amplifier
(OTA) is used whose design complexity and
power consumption are scaled exponentially with
the bandwidth. To support larger bandwidths and
higher number of antennas, a closed loop integrator
using ring amplifier [80], [81] was demonstrated in
[26]. Ring amplifiers are technology scalable lending
them good candidates to beamform signals from
even larger number of antenna elements. In contrast
to closed-loop amplifiers, summing can also be performed
through daisychain linked voltage-to-time
converter (VTC)s as shown in Fig. 17(b). The serialized
VTCs each acting in open-loop is digitized by a
multi-bit time-to-digital converter (TDC) creating an
equivalent of matrix-multiplying ADC.
3. Precision Clock Generation: The required sampling
phases of the discrete-time SSP can be
generated on-chip as illustrated in [22], [26]. To
achieve higher precision and matching following
Nyquist criterion as well as use the same architecture
for different SSP modes, the clock generation
requires N low-power precision phase
interpolator (PI) and time-interleavers [22], [51],
[52]. The time-interleaver output is applied to interleaved
multiply-and-accumulate units that enables
them to span the required delay range while
meeting the Nyquist bandwidth.
High precision linear PSs are desired to meet the delay
range and resolution requirements for the switchedcapacitor
array as discussed in Section III. Recent works
have demonstrated PIs as digital-to-phase generator in different
applications including clock-and-data recovery [82],
[83] and outphasing transmitters [84], [85]. In general, several
architectures have been proposed to implement PI
which generates output of phases of weighted sum of two
input clock phases based on the digital input code.
The underlying concept of PI can be studied from
[86] which describes the process as addition of two
phase-shifted edges to produce a new edge with the
transition in between them. The output is a superposition
of two exponential curves formed by the merged
driver output resistance and the capacitive load. The
linearity of the PI not only depends on the time difference
between the input signals but also their rise times.
It has been observed that the non-linearity for a step
input response is more whereas it is less for the inputs
with finite rise time inputs.
The current-steering digital-to-analog converter (DAC)
have been popular architectures for implementing PI [87].
However, the linearity and resolution are greatly impacted
by the DAC. As mentioned above, to generate finite rise
time at the input, a slew rate control buffer is implemented
which requires additional power. The summation of the
direct in-phase and quadrature-phase however causes
nonlinearity with respect to the codes. Alternatively, current-mode
logic based PI architectures can be adopted if
the inputs are sinusoidal signals. Instead of interpolating
between two consecutive quadrature phases, it can be
done in multiple cascaded stages. Interpolation between
signals with small phase differences (<45°) is more linear
than direct interpolation between the quadrature inputs.
Though the current-mode logic based PI has lower swing
which consumes less dynamic power, it suffers from linearity
issue where as the inverter-based PIs suffers from
high dynamic power. Additionally, the PI's output gets
affected by the power supply variations. Low-dropout
regulators can be applied between the main power supply
and the PI supply to alleviate this issue. As such, its important
to consider the design trade-offs for N PIs specifically
linearity and power consumption.
Figure 17. (a) amplifier based summing architecture, and
(b) time domain pipeline summing architecture.
18
IEEE cIrcuIts and systEms magazInE
B. Multi-Antenna Testbed and Validation
Another important step in the design process is developing
the test interface between the mmW front-end and
Fourth quartEr 2022
IEEE Circuits and Systems Magazine - Q4 2022

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2022
