IEEE Circuits and Systems Magazine - Q4 2022 - 27

1. Introduction
d
eep neural networks (DNNs) have grown rapidly in
importance in the past decade, enabling image recognition,
natural language processing, predictive
analytics, and many other tasks to be performed with high
accuracy and generalizability [40]. As the size and complexity
of DNNs have grown to tackle more challenging problems,
so has the demand for increasingly powerful and
energy-efficient processors. Hardware that is optimized for
DNN processing, which is dominated by matrix operations
[15], has been a major enabler of machine learning innovation.
But new, more efficient hardware approaches are
needed to keep pace with the rapid developments in artificial
intelligence and its growing computational needs [64].
Accelerators based on in situ computing-utilizing
memory for both storage and computation-have
attracted significant attention as a possible path to
order-of-magnitude improvements in energy efficiency
[9], [11], [56]. These systems harness the analog properties
of non-volatile memory arrays to perform many
concurrent multiply-and-accumulate (MAC) operations,
enabling the computation of a matrix-vector multiplication
(MVM) in a single step.
While analog processing offers intrinsic efficiency benefits,
it has historically struggled with accuracy. Unlike
digital systems, the solution quality in analog systems is
directly degraded by noise, process variations, and various
parasitic effects. To provide precision on par with
digital systems, many prior analog inference accelerators
adopt a hybrid approach known as bit slicing, where
weight values are spread bitwise across multiple memory
devices, and the analog intermediate results are digitized
and aggregated [9], [11], [56]. This technique allows weights
to be represented more precisely even with low-precision
memory devices, but at a higher energy cost than a purely
analog approach. Recent work has optimized the performance
and energy of bit-sliced accelerators [6], [14], [42],
[49], but rarely evaluates the effect of system-level design
decisions on inference accuracy.
This work studies how architecture affects accuracy
in analog inference accelerators. We use a detailed accuracy
model for in situ MVMs that includes the effect of
various analog errors at the resolution of individual
MACs, such as memory cell process variations and array
parasitic resistances. The model allows an architectural
design space exploration that uses the error sensitivity
of end-to-end inference accuracy as the primary
figure-of-merit. To provide a sensitivity analysis that
can be applied to realistic applications, accuracy is evaluated
on ImageNet classification with the ResNet50 neural
network from the MLPerf Inference benchmark. This
model is also used to benchmark digital systems [51].
Though the accuracy of analog accelerators has been
studied [65], the analysis in this work provides a more
comprehensive view of how accuracy fits into analog
architecture design. This work demonstrates that bit slicing
offers a smaller benefit than often assumed and typically
does not justify its energy cost; moreover, contrary
to the assumptions of prior work, bit slicing cannot be
used as a mitigation for highly error-prone analog devices.
Just as important, when signed arithmetic is handled in
analog, it is possible to obtain a linear or proportional
mapping between the numerical values in the algorithm
and the physical quantities that represent them in the
analog hardware. This proportionality is the key to enable
high inference accuracy and greater robustness to analog
errors. Following the end-to-end principle of Saltzer et al.
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