IEEE Circuits and Systems Magazine - Q4 2022 - 29

Table 1.
Comparison of data representation in selected prior work on analog in situ inference accelerators.
Accelerator
Genov et al. [21]
Memristive Boltzmann
Machine [9]
ISAAC [56],
Newton [49]
PUMA [6]
PRIME [11]
Dot-Product Engine [30]
Sparse ReRAM
Engine [66]
CASCADE [14]
TIMELY [42]
FORMS [69]
Marinella et al. [45]
Joshi et al. [34]
Yao et al. [67]
(experimental)
Guo et al. [24]
experimental)
Bit slicing
Yes, 1b/cell
Yes, 1b/cell
Yes, 2b/cell
Yes, 2b/cell
Yes, 4b/cell
No
Yes, 2b/cell
Yes, 1b/cell
Yes, 4b/cell
Yes, 2b/cell
No
No
No
No
Full
precision
No
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
No
No
No
No
Negative
weights
One's comp
Two's comp
Offset
Offset
Differential
Offset
Offset
−
−
Retrain
Differential
Differential
Differential
Differential
# rows
used per
MVM
128
32
128
128
256
128
16
64
256
8
1024
512
128
784
ADC
bits
BADC
6
5
8
8
6
4
6
10
8
4
8
8
8
analog
† The network is trained so that all weights on a column have the same sign. * Inputs are encoded in the temporal duration of a pulse.
states to overlap. The number of bits that can be
mapped to a cell is ultimately limited by the resolution
of the write circuitry and by the intrinsic physical
resolution of the cell.
2.2. Input Bit Slicing
Bit slicing can also be applied to multi-bit inputs; each
analog MVM processes one slice of
quantization is needed for all input bit slices [8], [14], [22].
Though feasible for 8-bit inputs, this technique cannot
be scaled to arbitrarily many input bits due to the thermal
noise floor on the analog signal.

x and the full input
is processed in multiple cycles. One-bit input slices are
commonly used to avoid the high overhead of a multibit
digital-to analog conversion (DAC) per input on each
MVM. A binary input voltage further allows the use of
memory devices with a nonlinear I − V curve, since ideally
only two points along this curve are sampled [61].
The cell configuration in Fig. 1(c) also relies on one-bit
input slices since the select gate functions as a binary
switch.
Partial MVM results from multiple input bit slices can
be aggregated digitally using a S&A reduction network,
similar to weight bit slices. The total number of ADC
quantizations required per full MVM (all weight and
input bits) is the product of the number of weight and
input slices. Alternatively, S&A accumulation of sequentially
applied input bits can be conducted by switchedcapacitor
circuits prior to the ADC, so that only one
fourth quartEr 2022
2.3. Handling Negative Numbers
A variety of techniques have been developed to
handle signed arithmetic with multi-bit weights and
inputs. This work evaluates the two most common
implementations of negative weights: offset subtraction
and differential cells. These schemes will be
described in more detail in Section 4.1. Offset subtraction
implements signed weights by including an offset
in the conductance used to represent a zero. This
then allows negative weights to be converted to positive
conductances. This offset then needs to be subtracted
from the dot product, either digitally or in the
analog domain [56].
In the differential cells scheme, a signed weight
is represented using the difference in conductance
of two memory cells. The specific implementation
of the subtraction varies across designs, and can be
performed in the analog domain or after digitization.
Analog current subtraction can be executed using
opposite-polarity voltage inputs and Kirchoff's law
IEEE cIrcuIts and systEms magazInE
29
DAC bits
1
1
1
1
3
4
1
1
8
1
1
8
1
1

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