IEEE Circuits and Systems Magazine - Q4 2022 - 30

[45], or within the bit line peripheral circuitry [24],
[34], [67]. Though this scheme uses two cells per
weight (or per weight slice) rather than one, it possesses
important advantages over offset subtraction,
as summarized in Section 3.
Negative inputs can be handled by applying negative
voltages to a resistive array [45], or by using
two differential pairs (four cells) per weight [7], [54].
Notably, negative inputs are uncommon beyond the first
layer of convolutional neural networks (CNNs) based on
rectified linear (ReLU) activations. If both weights and
inputs use one-bit slices, it is possible to use a two's
complement representation for both [9].
2.4. Full Precision Guarantee
The conversion of an analog dot product to a digital
result can incur a loss of precision. To provide theoretically
digital accuracy from an analog MVM, prior work
proposed the full precision guarantee (FPG) [9], [56].
The FPG posits that if the ADC has a unique level for
every possible output of the MVM operation, then there
is no loss of information from digitization. The information
content of the analog signal, equal to the number of
bits needed to specify all possible dot product values,
is a function of the operand widths and the number of
summed terms [56]:
B
BB NB B
out BB N
2

WinW in
Win
1
2
2
logif
logotherwise
33,11
(2)
where BW is the number of weight bits per cell, Bin is the
number of input bits per ADC operation, and N is the
number of rows activated in an MVM. Notably, if input
bit slices are accumulated digitally, Bin is the number of
input bits per slice; if they are accumulated by analog
circuitry, Bin is the smaller of the full input resolution or
the circuit's resolution. A non-integer value of Bout simply
means that the number of possible MVM outputs is
not a power of two.
The FPG can be stated as:
BB
ADC = out
(3)
where BADC is the ADC effective number of bits. Typically,
Bin, BW and N are chosen such that Bout ≈ 8 bits.
Since the ADC cost rapidly becomes prohibitive with
resolution [48], prior work using the FPG has been
limited to smaller arrays and/or fewer bits per weight.
Shafiee et al. [56] proposed a 'flipped' encoding of
weight values to reduce the required ADC resolution to
Bout − 1 bits.
In many systems, the final result after aggregating all
slices is truncated before being passed to the next layer.
This means that not all Bout bits from every slice are
30
IEEE cIrcuIts and systEms magazInE
useful. Prior work has proposed avoiding this wasted
computation by dynamically tuning the ADC resolution
on a slice-wise basis [11], [49].
As shown in Table 1 , not all systems adopt the
FPG. This design choice will be evaluated in Sections
3 and 6.
2.5. Direct Weight Transfer Versus Retraining
To improve inference accuracy in the presence of analog
errors, many methods have been proposed to integrate
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