IEEE Circuits and Systems Magazine - Q4 2022 - 33

Figure 5. four schemes for mapping weight values to conductance values in a memory array. numerical labels on the
memory elements are in ascending order from the minimum conductance state (0) to the maximum conductance state (2N-1 for
an N-bit cell).
programmed onto the conductances of two sets of memory
cells. This definition leaves some ambiguity about how
two conductances are decided from a single weight value.
This paper evaluates the convention where one cell in the
pair encodes the magnitude of positive weights, while the
other encodes the magnitude of negative weights. This
means that at least one cell in every pair is left in the lowest
conductance state. Note that the weight magnitudes in
this scheme are directly mapped to the conductances of
7-bit cells, ensuring a proportional mapping.
The integer values in the non-negative matrices on
the right sides of Equations (4) and (5) are mapped linearly
to conductances. A value of 0 is mapped to the
minimum conductance state Gmin, while the maximum
value in the range is mapped to Gmax. Intermediate integers
are linearly mapped to intermediate conductances.
4.1.2. Mapping with Bit Slicing
Fig. 5(c) shows an example of offset subtraction with bit
slicing, which implements the following mapping:
WW WW W
  
xx xx xx
2
4
2
3
2
10
22 226
7I
(6)
where Wi are the 2-bit slices of W from lowest to highest
significance. Each element of Wi is integer-valued
in the range [0,3] and mapped to the conductance of a
single cell. The offset is subtracted after the results of
the slices are aggregated. As in the non-bitsliced case,
this is not a proportional mapping, since a zero weight is
mapped to an intermediate conductance in the top slice.
Fig. 5(d) shows an example of differential cells with
bit slicing, which implements the following mapping:
WW WW W
WW W
  
 
xx xx x
xx x
2
22
2
33
fourth quartEr 2022
6
2
22
11 0 W0
4
x
(7)
where each 2-bit matrix Wi
± is integer-valued in the
range [0,3]. This method uses a sign-magnitude representation
and slices the magnitude bits across multiple
cells. Within a slice, the magnitudes of positive
weights are mapped to Wi
negative weights are mapped to Wi
+ and the magnitudes of
-, and the resulting
bit line currents are subtracted. The most significant
slice is proportional to the weight value, and a
zero weight is mapped entirely onto the '0' state in all
slices, as shown in Fig. 5(d). Because the four slices
together represent 8 magnitude bits, the configuration
in Fig. 5(d) can map a 9-bit signed weight in the
range [−255, +255].
4.1.3. Input Bit Accumulation
For all of the schemes above, one-bit input slices are
assumed to simplify the input DAC and device requirements.
For differential cells, results from different
input bits are sequentially accumulated using analog
circuitry as described in Section 2.2, such that Bin =
8 bits. For offset subtraction, analog accumulation
requires summing all of the 8-bit elements of the input
vector

x to compute the offset, which is more complex
than summing the elements of

xQ
one bit at a time. To
avoid this overhead and to provide a baseline that is
similar to prior work [6, 49, 56], offset subtraction is
evaluated with digital S&A accumulation of input bits
(Bin = 1 bit).
4.2. Accuracy Simulation of Analog MVMs
For a realistic accuracy simulation of an analog inference
accelerator, we extend CrossSim [4] with a highly
parameterizable model for an analog MVM array.
CrossSim imports a Keras neural network model [13]
and maps the weight matrix of each convolution and
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