IEEE Circuits and Systems Magazine - Q4 2022 - 42

Figure 20. Bit line currents vs array size and mapping for
resnet50-v1.5. Layers that use the same # rows are averaged
together. Inputs are applied bit-wise based on the cell
in fig. 1(c), and results are computed for the input LsB, which
activates the most rows. the cell current varies from 0 to
Imax = 1.6µa (infinite on/off ratio).
distribution network (VD). Thus, only the parasitic resistance
of the bit line is considered, whose value between
two adjacent cells is denoted Rp. The bottom of the bit
line is held at virtual ground by the peripheral circuitry,
such as a current integrator [45] or transimpedance
amplifier [41]. For computational tractability, neural
network simulations use the approximate circuit in
Fig. 21(b). Select transistors are modeled as ideal
switches, and a small-signal approximation is made to
model the memory devices as linear resistors. To generalize
to any memory cell or metal interconnect technology,
the sensitivity analysis uses the normalized
parasitic resistance Rp
ˆ , defined as the ratio of Rp to the
minimum cell resistance 1/Gmax.
When applying inputs one bit at a time, the effect of
parasitic resistance varies considerably with bit position.
This is because activations are typically skewed
heavily toward low values, which makes the higher bits
more sparse [47]. The lower bits have less sparsity, activate
more rows, and have the largest parasitics-induced
errors. However, these errors are suppressed to some

IEEE Circuits and Systems Magazine - Q4 2022

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